Shivam katiyarAI tools for Design & VerificationI will discuss the current AI tools available in the market specifically for design and verification. It’s challenging to find open-source…Jul 13Jul 13
Shivam katiyarGLS in the Verification FlowLet’s explore the essential requirements for setting up a GLS test bench.Jul 8Jul 8
Shivam katiyarHow to integrate RAL in TestbenchThis topic holds immense popularity across various testbenches when verifying any design. I will guide you through a systematic…Jan 23Jan 23
Shivam katiyarConfigDB: The Heart of UVMThis article is for engineers who are new to verification methodologies or are in the process of adopting UVM, this focuses on the UVM…Oct 30, 2023Oct 30, 2023
Shivam katiyarUnraveling the Magic: How UVM Factory Transforms Testbench DesignThe UVM testbench is great for reusing code, but when you want to reuse it for different things, like changing how data is sent and…Oct 13, 2023Oct 13, 2023
Shivam katiyarImportance of virtual sequence and sequencerTests that need to generate stimulus in a coordinated manner using multiple drivers must use virtual sequences.Oct 7, 2023Oct 7, 2023