Inter-Integrated Circuits — I2C Basics (Part 3)
Case 1: Master (Transmitter) to Slave (Receiver) Data Transfer
Let’s have a look at the entire transaction first and then analyze it.
- The Master sends the START sequence to begin the transaction.
- It is followed by Master sending 7-bit Slave address and the R/W’ bit set to zero. We set it to zero because the Master is writing to the Slave.
- The Slave acknowledges by pulling the ACK bit low.
- Once the Slave acknowledges the address, Master can now send data to the Slave byte-by-byte. The Slave has to send the ACK bit after every byte it receives.
- This goes on till Slave can no longer receive data and does NOT send the ACK bit.
- This is when the Master realizes that the Slave has gone crazy (not accepting anymore) and then STOPs the transaction (or reSTART).
We see that the data transfer never changes its direction. Data always flows from Master to Slave, which makes the setup quite easy.
An example of this case would be like performing page write operations on a EEPROM chip.
Case 2: Slave (Transmitter) to Master (Receiver) Data Transfer
Let’s look at the entire transaction again.
- The Master sends the START sequence, followed by the 7-bit Slave address and the R/W’ bit set to 1.
- We set R/W’ bit to 1 because the Master is reading from the Slave.
- The Slave acknowledges the address, thus ready to send data now.
- Slave keeps on sending data to the Master, and the Master keeps on sending ACK to the Slave after each byte until it can no longer accept any more data.
- When the Master feels like ending the transaction, it does not send the ACK, thus ending with the STOP sequence.
An example of this case could be an Analog to Digital Converter (ADC) sending data to the microcontroller continuously. The microcontroller accepts data as long as it wants to, after which it stops/finishes execution.
Case 3: Bi-directional Read and Write in same Data Transfer
Once again, let’s look at the entire transaction first!
- The Master sends out the START sequence, followed by the 7-bit Slave address and the R/W’ bit.
- The Slave acknowledges the address.
- Depending upon the value of the R/W’ bit, read/write operations are performed (like the above two cases).
- Whatever the case it may be, it always ends with the receiver not sending the ACK.
- Until now, in the previous two cases, we have seen that the Master would close the connection. But in this case, the Master attempts a repeated START.
- And the entire process repeats again, until the Master decides to STOP.
As we can see, a change of direction of data transfer might happen depending upon the R/W’ bits in the entire transaction.
An example of this case could be performing sequential read from a EEPROM chip. It is bi-directional because the CPU first writes the address from where it would like to start reading, followed by reading from the device. It is like, unless you tell the device from where you would like to start reading, how would it start sending you the data?
Clock Stretching
So far so good. Now let’s look at a very plausible complication. Suppose Master is reading data from the Slave. Everything goes on good as long as the Slave returns the data. What if… what if the Slave is not just ready yet? This is not an issue with devices like ADC or EEPROM, but with devices like a microcontroller. What if the Slave is a microcontroller, and the Master requests for a data which is not there in its cache. This would require the microcontroller to perform context switching, force it to search for it in the RAM, store it back in cache and then send it to the Master. This could (and definitiely would) take a much longer time than the clock pulses of the SCL, and everything would just go wrong!
Fortunately, there is a way, called Clock Stretching. The Slave is allowed to hold the clock line low until it is ready to give out the result. The Mastermust wait for the clock to go back to high before continuing with its work.
This is the only instance in the entire I2C protocol where the Slave is drives the clock line SCL. In many processors and microcontrollers, the low level hardware does this for us, so that we don’t have to worry about it while writing the code.
Why I2C?
Now that we are almost done with the basics of I2C communications, let’s take a moment to jot down some advantages of I2C.
- I2C requires least number of pins (just two pins) to perform serial data transfer.
- The receiver always sends feedback to the transmitter (ACK) conveying a successful transmission, which leads to higher noise immunity as well.
- Even though it has a slow standard speed of 100 kHz, modern I2C specifications support up to 3.4 MHz clock speed.
Summary
- I2C is an 8-bit bidirectional synchronous serial communication protocol requiring only two wires for operation.
- The I2C bus consists of two open-drain lines — SDA (data) and SCL (clock).
- Several devices, being either Master or Slave, can be connected to the bus. The Master device must initiate the transfer and drive the clock line (SCL).
- I2C supports the standard speed of 100 kbps, up to a maximum speed of 3.4 Mbps.
- Master must generate unique Start and Stop conditions in order to mark the beginning and end of a transaction.
- The receiver must send the ACK bit after every byte that it receives, failing which the Master may either Stop the transaction or attempt a repeated Start.
- Every device connected to the I2C bus has either 7-bit or 10-bit address. An additional R/W’ bit is added to the address by the Master to determine whether it wants to read or write from/to the device.
- Data transfer can be unidirectional (Master to Slave OR vice-versa) or bidirectional.
- Slave can hold the clock line low until it is ready with the result to be sent to the Master, called Clock Stretching.
My story right now.
- Designing and developing EPS for Cubesats.
- I’m in my final semester of my engineering degree, so kinda chillin out at home.
- Book I’m looking forward to read right now is The Mamba Mentality by Kobe Bryant.
See you next time
SS
Thanks for reading.
Until next time
Peace, Love and Gratitude.
