So, the first thing to do is probably to get the CPU powered and in the proper state to run. Let’s look at the 6502’s pinout, available here in its datasheet.
Let’s supply our power first. The FPGA board will be providing our power. First we connect the voltage input (VDD) and ground (VSS).
After that, there’s a few control signals that we need to keep tied high for now. RDY decides whether the CPU executes instructions, so we hold that high. IRQB prompts an interrupt when it’s set low, so we’ll tie that high for now until we need it later. BE enables the address and data buses, and so we tie that high. SOB is not recommended to be used, and we’re best off just tying it high.
RESB handles resetting the CPU. When goes from low to high, the CPU undergoes a reset sequence that we will talk about shortly. For now, we will attach it to a button.
Lastly, we will look at the PHI2 pin. The PHI2 pin is the main clock input, and when the clock changes from positive to negative the 6502 ticks over to its next cycle. This we will leave unconnected until the second part, where we create some FPGA code to generate this clock signal.
