Understanding the CHI Protocol: Achieving High-Performance Coherency

AMBA PROTCOLS

Introduction

The Coherent Hub Interface (CHI) protocol is designed for advanced SoC (System-on-Chip) environments where multiple processors, memory controllers, and other components need efficient communication with full cache coherency support. CHI, part of the AMBA 5 protocol family, is an upgrade from ACE (AXI Coherency Extensions), offering improved scalability, efficiency, and coherency for large-scale multi-core systems.

This article covers all key signals, data flow, address handling, and handshaking mechanisms, along with advanced features of the CHI protocol.

CHI Protocol Overview

CHI manages communication between multiple masters (such as CPUs, GPUs, AI accelerators) and slaves (memory controllers, caches, I/O devices). The protocol uses packet-based transactions, ensuring that data, control, and address information are transmitted efficiently.

1. Key Features of the CHI Protocol

• Packet-Based Transactions: Command, data, and response signals are transmitted as distinct packets.
• Multiple Layers: CHI organizes communication into three layers: Request, Data, and Response, each responsible for different aspects of transaction…