INTERRUPT IN THE 8085 MICRO-PROCESSOR:
1. INTRODUCTION:
· 1.1. DEFINITION OF INTERRUPT:
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor and get itself serviced. Generally, a particular task is assigned to that interrupt signal. In the microprocessor based system the interrupts are used for data transfer between the peripheral devices and the microprocessor. In simple words, Interrupt may be said as
· The process starts from the I/O device
· The process is asynchronous.
· An interrupt is considered to be an emergency signal that may be serviced.
· The Microprocessor may respond to it as soon as possible.
· 1.2. INTERRUPT IN THE 8085 MICRO-PROCESSOR:
When microprocessor receives any interrupt signal from peripheral(s) which are requesting its services, it stops its current execution and program control is transferred to a sub-routine by generating CALL signal and after executing sub-routine by generating RET signal again program control is transferred to main program from where it had stopped.
When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the peripheral which is requesting for its service.
· 1.3. CHANGES WHEN MICRO-PROCESSOR IS INTERRUPTED:
When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR.
· 1.4. WHAT IS INTERRUPT SERVICE ROUTINE(ISR):
A small program or a routine that when executed services the corresponding interrupting source is called as an ISR. Each interrupt will most probably have its own ISR.
2. FAMILIARIZATION OF INTERRUPTS IN 8085:
· 2.1. PROCESS OF INTERRUPTS:
When the interrupt signal arrives:
· The processor will break its routine
· Go to a different routine (interrupt service routine)
· Complete the interrupt service routine (ISR)
Go back to the “regular” routine in order to execute an interrupt routine, the processor:
· should be able to accept interrupts (interrupt enable)
· Save the last content of the program counter
· Know where to go in program memory to execute the ISR
· Tell the outside world that it is executing an interrupt
· Go back to the saved PC location when finished.
· Interrupts increase processor system efficiency by letting I/O device request CPU Time only when that device needs immediate attention.
· An interrupt is a subroutine call initialized by external hardware.
· The request is asynchronous
· It may occur at any point in a program’s execution.
· 2.2. DIAGRAM:
3.CLASSIFICATION OF INTERRUPTS:
3.1.HARDWARE AND SOFTWARE INTERRUPTS: –
When microprocessors receive interrupt signals through pins (hardware) of microprocessor, they are known as Hardware Interrupts. There are 5 Hardware Interrupts in 8085 microprocessor. They are — INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
Software Interrupts are those which are inserted in between the program which means these are mnemonics of microprocessor. There are 8 software interrupts in 8085 microprocessor. They are–RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
Interrupts can be classified into two types:
Maskable Interrupts (Can be delayed or Rejected)
Non-Maskable Interrupts (Cannot be delayed or rejected)
Interrupts can also be classified into:
Vectored (the address of the service routine is hard-wired)
Non-vectored (the address of the service routine needs to be supplied externally by the device)
3.2. MASKABLE AND NON-MASKABLE INTERRUPTS:
Maskable Interrupts are those which can be disabled or ignored by the microprocessor. These interrupts are either edge-triggered or level-triggered, so they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085 microprocessor.
Non-Maskable Interrupts are those which cannot be disabled or ignored by microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well as edge triggering and is used in critical power failure conditions.
o MP completes its current machine cycle.
o There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored.
3.3.VECTORED AND NON-VECTORED INTERRUPTS :
Vectored Interrupts are those which have fixed vector address (starting address of sub-routine) and after executing these, program control is transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE
Non-Vectored Interrupts are those in which vector address is not predefined. The interrupting device gives the address of sub-routine for these interrupts. INTR is the only non-vectored interrupt in 8085 microprocessor.
4. RESPONSE TO INTERRUPT:
4.1. 8085 INTERRUPT STRUCTURE :
There are 5 interrupt inputs:
o TRAP (non-maskable)
o RST7.5
o RST6.5
o INTR
o RST 5.5
4.2. RESPONSE TO INTERRUPT:
· Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not.
· MP completes its current machine cycle.
· There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored.
PROCESS:
1. The processing of the current instruction is completed.
2. An interrupt machine cycle is executed during which the PC is saved and control is
transferred to an appropriate memory location.
3. The state of the MPU is saved.
4. If more than one I/O device is associated with the location transferred to, the highest priority device requesting an interrupt is identified.
5. A subroutine is executed which services the interrupt I/O device.
6. The saved state of the microprocessor is restored.
7. Control is returned to the instruction that follows the interrupted instruction.
5. INSTRUCTION FOR INTERRUPTS –
5.1. ENABLE INTERRUPT (EI) :
The interrupt enable flip-flop is set and all interrupts are enabled following the execution of next instruction followed by EI. No flags are affected. After a system reset, the interrupt enable flip-flop is reset, thus disabling the interrupts. This instruction is necessary to enable the interrupts again (except TRAP).
5.2. DISABLE INTERRUPT (DI) :
This instruction is used to reset the value of enable flip-flop hence disabling all the interrupts. No flags are affected by this instruction
5.3. SIM INSTRUCTION:
It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate output data via the Serial Output Data (SOD) line. First the required value is loaded in accumulator then SIM will take the bit pattern from it.
Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is the mask for
RST 7.5.
If the mask bit is 0, the interrupt is available.
If the mask bit is 1, the interrupt is masked.
Bit 3 (Mask Set Enable — MSE) is an enable for setting the mask.
If it is set to 0 the mask is ignored and the old settings remain.
If it is set to 1, the new setting are applied.
Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.5 memory even if the microprocessor did not respond to it.
Bit 5 is not used by the SIM instruction
Bit 6 & Bit 7 is used for extra functionality such as serial data transmission.
Example: Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5 is enabled.
First, determine the contents of the accumulator.
EXAMPLE:
· Set the interrupt masks so that RST 5.5 is enabled, RST 6.5 is masked and RST 7.5 is enabled.
· First, determine the contents of the accumulator.
- Enable 5.5 bit 0=0
- Disable 6.5 bit 1=1
- Enable 7.5 bit 2=0
- Allow setting the masks bit 3=1
- Don’t reset the flip-flop bit 4=0
- Bit 5 is not used bit 5=0
- Don’t use serial data bit 6=0
- Serial data is ignored bit 7=0
EI ; Enable interrupts including INTR
MVI A, OA; Prepare the mask to enable RST 7.5 and 5.5, disable 6.5
SIM ; Apply the setting RST masks
5.4. READ INTERRUPT MASK (RIM):
This instruction is used to read the status of the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte which defines the condition of the mask bits for the interrupts. It also reads the condition of SID (Serial Input Data) bit on the microprocessor showing the status of each interrupt pin and mask.
Load the accumulator with an 8-bit pattern
Bits 0–2 show the current setting of the mask for each of RST 7.5, RST 6.5 and RST 5.5 .They return the contents of the three mask flip flops.
•Bit 3 shows whether the maskable interrupt process is enabled or not.
It can be used by a program to determine whether or not interrupts are enabled.
•Bits 4–6 show whether or not there are pending interrupts on RST 7.5, RST 6.5,and RST 5.5 .
•Bit 7 is used for Serial Data Input.
The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit.
•Microprocessor can be interrupted again before the completion of the ISR.
•As soon as the 1st interrupt arrives, all maskable interrupts are disabled.
•They will only be enabled after the execution of the EI instruction.
- If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done.
6. WORKING PRINCIPLES OF INTERRUPTS -
6.1. THERE ARE 6 PINS AVAILABLE IN 8085 FOR INTERRUPT:
•TRAP
• RST 7.5
• RST6.5
• RST5.5
• INTR
•INTA
6.2. EXECUTION OF INTERRUPTS:
When there is an interrupt requests to the Microprocessor then after accepting the interrupts Microprocessor send the INTA (active low) signal to the peripheral. The vectored address of particular interrupt is stored in
program counter. The processor executes an interrupt service routine (ISR) addressed in program counter.
There are two types of interrupts used in 8085 Microprocessor:
1) Hardware Interrupts, 2) Software Interrupts
6.2.1. HARDWARE INTERRUPT:
As I have already discussed that there are 6 interrupt pins in the microprocessor used as Hardware Interrupts given below:
1. TRAP
2. RST7.5
3. RST6.5
4. RST5.5
5. INTR
6.2.2. SOFTWARE INTERRUPTS:
A software interrupts is a particular instructions that can be inserted into the desired location in the program. There are eight Software interrupts in 8085 Microprocessor from RST 0 to RST 7.
RST0
RST1
RST2
RST3
RST4
RST5
RST6
RST7
They allow the microprocessor to transfer program control from the main program to the subroutine program. After completing the subroutine program, the program control returns back to the main program.
We can calculate the vector address of these interrupts using the formula given below:
Vector Address = Interrupt Number * 8
For Example:
RST2: vector address=2*8 = 16
RST1: vector address=1*8 = 08
RST3: vector address=3*8 = 24
6.3. NON-VECTORED INTERRUPT:
1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA(Interrupt acknowledge) signal to the device that interrupted .
4. INTA allows the I/O device to send a RST
instruction through data bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the program is transferred to ‘call’ location (ISR Call) specified by the RST instruction.
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the further interrupt within the program.
8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.
9. Although INTR is a maskable interrupt, it does NOT need SIM to get enabled.
Just instruction EI is enough.
The 8085 recognizes 8 RESTART instructions: RST0 — RST7.
6.3. VECTORED INTERRUPTS:
6.4.1. TRAP:
It is non maskable edge and level triggered interrupt. TRAP has the highest priority and vectors interrupt. Edge and level triggered means that the TRAP must go high and remain high until it is acknowledged. In case of sudden power failure, it executes a ISR and send the data from main memory to backup memory.
As we know that TRAP can’t be masked but it can be delayed using HOLD signal. This interrupt transfers the microprocessor’s control to location 0024H. Trap Interrupt can also be masked by resetting the microprocessor. There is no other way to mask it.
6.5. TRIGGERING LEVELS:
RST 7.5 is positive edge sensitive.
When a positive edge appears on the RST7.5 line, a logic 1 is stored in the flip-flop as a “pending” interrupt.
Since the value has been stored in the flip flop, the line does not have to be high when the microprocessor checks for the interrupt to be recognized.
The line must go to zero and back to one before a new interrupt is recognized.
RST 6.5 and RST 5.5 are level sensitive.
The interrupting signal must remain present until the microprocessor checks for interrupts.
•TRAP is the only non-maskable interrupt.
•It does not need to be enabled because it cannot be disabled.
•It has the highest priority amongst interrupts.
•It is edge and level sensitive.
•Must make a low-to-high transition and remain high to be acknowledged.
•After acknowledgement, it is NOT recognized again until it goes low, then
high again and remains high.
•It is to avoid false triggering due to noise/logic glitches.
•TRAP is usually used for power failure and emergency shutoff.
When the 8085A is reset:
Its internal interrupt enable flip-flop is reset. This disables ALL the maskable interrupts. So, the MPU only responds to TRAP. Vectored address for TRAP is 0024 H.
7. RESTART AS SOFTWARE INTERRUPT:
7.1. RESTART SEQUENCE:
•The restart sequence is made up of three machine cycles
•In the 1st machine cycle: The Microprocessor sends the INTA signal.
•While INTA is active the microprocessor reads the data lines expecting to receive, from the interrupting device, the opcode for the specific RST instruction.
•In the 2nd and 3rd machine cycles: the 16-bit address of the next instruction is saved on the stack.
•Then the microprocessor jumps to the address associated with the specified RST instruction.
•There are 8 different RST instructions.
• Each RST instruction tells the processor to go to a specific memory address (call
location — fixed).
7.2. READING THE RST5 INSTRUCTION:
The above example is for generating RST 5:
RST 5’s op code is EF =11101111
7.3. HARDWARE GENERATION OF RST OPCODE:
During the interrupt acknowledge machine cycle,(the 1st machine cycle of the RST operation):
The Microprocessor activates the INTA signal.
This signal will enable the Tri-state buffers, which will place the value EFH on the data
bus.
Therefore, it is sending the Microprocessor the RST 5 instruction.
The RST 5 instruction is exactly equivalent to CALL 0028H
8. SOME IMPORTANT INTERRUPTS-
8.1. INTR INTERRUPT:
The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction.
The INTR line must be deactivated before the EI is executed. Otherwise, the microprocessor will be interrupted again.
Once the microprocessor starts to respond to an INTR interrupt, INTA becomes active (=0).Therefore, INTR should be turned off as soon as the INTA signal is received. response to the acknowledge signal,
external logic places an instruction OPCODE on the data bus. In the case of multi byte instruction, additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes into the
Microprocessor.
On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction.
The Programmable Interrupt Controller (PIC) functions as an overall manager in an Interrupt-Driven system environment. It accepts requests from the peripheral equipment, determines which of the in-coming requests is of the highest priority.
The 8259A is a device specifically designed for use in real time, interrupt driven microcomputer systems.
It manages eight levels or requests and has built in features for expandability to other 8259A’s (up to 64levels). It is programmed by the system’s software as an I/O peripheral.
Each peripheral device usually has a special program or ``routine’’ that is associated with its specific functional or operational requirements; this is referred to as a ``service routine’’.
The PIC, after issuing an Interrupt to the CPU, must somehow input information into the CPU that can ``point’’ the Program Counter to the service routine associated with the requesting device. This ``pointer’’ is an address in a vectoring table and will often be referred to, in this document, as vectoring data.
•Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain pending.
•Using the RIM instruction, it is possible to read the status of the interrupt lines and find if there are any pending interrupts.
8.2. PENDING INTERRUPTS:
Since the 8085 has 5 interrupt lines, interrupts may occur during an ISR and remain pending. Using the rim instruction, it is possible to read the status of the interrupt lines and find if there are any pending interrupts.
8.3. MULTIPLE INTERRUPTS:
•There are 8 different RST Instructions .
•How do MPU allow multiple devices to interrupt using the INTR line?
•The microprocessor can only respond to one signal on INTR at a time.
•Therefore, we must allow the signal from only one of the devices to reach the microprocessor.
- We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority.
- The solution is to use a circuit called the priority encoder as opcodes for the different RST instructions follow a set pattern.
- When microprocessor receives multiple interrupt requests simultaneously, it will execute the interrupt service request (ISR) according to the priority of the interrupts.
