Wei-Yuan,Weng ( Victor)Static Timing Analysis _(2) _Derive the formula for timing constraintRegarding STA, the follow-up description will be added, the STA description of the classic timing. The following figure shows the classic…Apr 2, 2022Apr 2, 2022
Wei-Yuan,Weng ( Victor)Cell-Based IC Design flow_VictorThere should have many typo or incorrect grammar. But I’ll try to write in English. Hope that everyone can considerate my fault.Feb 18, 2022Feb 18, 2022
Wei-Yuan,Weng ( Victor)TCL --------前言介紹TCL的全名為Tool Command Language,稱”Tickle語言”,事實上它是一個腳本語言(Scripting Language)。Jan 18, 2022Jan 18, 2022
Wei-Yuan,Weng ( Victor)Low Power Design (FPGA/ASIC/硬體設計理論篇)最近研替上班還在忙做類似Design House SA的事情 ,AUO_EE算是很不錯的公司,讓我能在下班多多複習額外的知識,剛菜鳥就接新機種的案子,最近在忙跟LG開會,韓國人真難搞!,比較少時間準備複習low power。Jan 14, 2022Jan 14, 2022
Wei-Yuan,Weng ( Victor)靜態時序分析(Static Timing Analysis ,STA)這篇來記錄自學實際應用,靜態時序分析(STA),意指是在數位電路設計工程中,對時序(timing)進行估算的流程。Dec 24, 2021Dec 24, 2021
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Wei-Yuan,Weng ( Victor)ㄔㄧ// — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — // // Engineer : Wei-Yuan, Weng (Victor.Weng)…Nov 29, 2021Nov 29, 2021
Wei-Yuan,Weng ( Victor)Panel 顯示_timing(實戰)--(1)邊上班邊教學複習有點累,犧牲午休/吃飯時間,這邊稍微複習顯示timing的硬體怎麼寫。Nov 28, 2021Nov 28, 2021
Wei-Yuan,Weng ( Victor)進階技巧-Clock Domain Crossing(CDC) (FPGA/ASIC -design)— — — — — — — — — — — — — — — -(2) — — — — — — — — — — — — — —Nov 27, 2021Nov 27, 2021
Wei-Yuan,Weng ( Victor)進階技巧-Clock Domain Crossing(CDC) (FPGA/ASIC -design)-------------------------------------基礎邏輯電路---------(1)Nov 26, 2021Nov 26, 2021