ARM Architecture: What are the Differences Between ARMv7 and ARMv8 ARM Architectures

When talking about ARMv7 and ARMv8 we need to specify as well the processors families, as we have ARMv7M/ARMv8M covering the Cortex-M processors families and ARMv7A/ARMv8A covering the Cortex-A processors families.

So for Cortex-M , the major difference between ARMv7M and ARMv8M is Trust-Zone:

• Armv8m introduced the Trust-Zone support to allow arm TEE (Trusted Execution Environment) security model, so we will have instead extra two states added to CPU secure and non-secure state
• Beside secure and non-secure state the physical address space will be divided into 2 spaces: secure Physical and non-secure physical address spaces.
• Two Hardware blocks has been added to Processor block allowing secure/non-secure attribute assignment for Physical memories: SAU (Security Attribute Unit) and IDAU (Implementation Defined Attribution Unit) which offer more flexibility for software to split secure/non-secure binaries based on address space assignment.
• we will have as well secure and non secure interrupt supports, couple of system registers like VTOR or SCB based registers are banked between security states.
• In term of CPU internal registers we will have 4 stack pointers support instead of 2 in armv7m, Secure MSP/non-secure MSP, Secure PSP/non-secure PSP, so stack pointer register is banked between security state
• Same thing for CPU modes, thread and handler modes are banked between security states
• Extra instruction has been added to armv8m compared to armv7m to allow the switch back and forth between secure and non secure states like; BXNS/BLXNS/SG(Secure Gate)
• M33/M23 which are armv8M based Micro-Processor can support some dual issues execution style for some specific instruction Like NOP instructions
• MPU configuration is different than armv7m, so configuration is split in different registers field and we can have multiple configuration available at same time which is different concept than armv7m where the configuration of the memory region is part of the defined MPU memory region and not defined separately.

Going now to Cortex-A based architecture, there are quiet significant difference between armv7A and armv8A:

• Armv8A has the new support of execution state AARCH64 but has support as well of legacy AARCH32 nevertheless this is for old/mid level Cortex-A processor the new ones mostly has only support for AARCH64.
• The way Exception levels are treated is different between AARCH32 and AARCH64, so in AARCH32 Cortex-A has mode based abstraction, so we have modes like IRQ mode, IRQ mode, System Mode, User mode, Hypervisor Mode, …., in AARCH64 execution state it is Exception level based abstraction: so we will have 4 Exception levels (EL0/EL1/EL2/EL3) and each one is kind of separated sandbox with its own banked system registers, the only exception will be EL3 that is acting as Gatekeeper to control the security state switch of each Exception level
• On AARCH32 the Hypervisor used for virtualization is running on Hyp non secure mode always so hypervisor will not execute in secure, however starting from armv8A in AARCH64 Exception level we can have secure EL2 and EL2 is the Exception Level where the Hypervisor (or Hosted Os in case VHE is enabled for hypervisor type 2 support will be always executing there
• while running on AARCH64 Execution state, the cpu register width will be 64 bits instead of 32 bits while in AARCH32, and there are many instruction can execute execute on AARCH64 but not in AARCh32

The difference are quiet big specially in Cortex-A based processor family therefore I recommend to check always the reference manual as well as ARM developer Website:

Arm Developer