ARM Core: Memory Management Unit (MMU)
MMU or Memory management unit serves to virtualize address space used by running program and this allow to achieve certain level of multi-processing which will not possible without virtualizing the Physical address space, not only that it allows to provide memory space range that Internal Physical doesn’t have which allow running as many program as external hard disk can store.
- Virtual to Physical Address: when it comes to addressing we have always 2 major issues: we want contiguous address space that can be used by our process and we want as such as we can to fit big number of running process, using only Physical address doesn’t help here ad internal Physical address is limited in term of size and also we will have issue of external fragmentation which prevents allocating contiguous address space to single process , and the way to go to solve such issues is by virtualizing the address space used by the process. the Translation of Virtual address to Physical one is done through the MMU but MMU needs certain input and block before performing such translation
Above is ARM implementation of MMU, first we need to know that MMU will requires a translation table to be able to do the mapping between Virtual and Physical address, so each VA will use its upper bits to identify the entry within the translation table to pickup then what is left will be used as an offset to be appended to physical address returned by the translation table entry:
VA : 0x01000010 (32 bits address) -> bits[31:24] = 0x01 -> select entry in TTB (Translation Table)
TTB[1] = 0x80000000 (Physical address) MSB part
VA : 0x01000010 -> TTB -> 0x80000000 | 000010 = 0x80000010 (PA)
This is simplified example of course because we may have some extra settings associated with TTB entry and not only 32 bits base Physical Address available (read/write/execute restriction or Memory attribute access like normal/device/strongly ordered in arm)
To speed up access to TTB a dedicated cache Memory has been added for such purpose which is called Translation Lock-Aside buffer (TLB) and first thing MMU will do is to check the TLB before doing Table Walk-in as this is costly to go all the way to physical memory to get TTB corresponding address.
- Paging: this is more something handled by Operating System not MMU itself, but MMU offers the possibility to do such concept, as you noticed above having first VA MSBs used to select TTB entry means the Virtual Address space get divided into equal sized memory blocks, and each block has single TTB entry, doing such thing allow easy manipulation of such block as the have each fixed size + single entry on TTB to be used for address mapping between VA and PA , nevertheless when running many process we may have not sufficient PA to hole all of them so what OS is doing is just doing what is called paging by putting not active process VA blocks (or let’s say their corresponding PA blocks) into external Had disk and it keeps only PA blocks used by active space so overall timeline we may have two process sharing same Physical Address Space but at one moment of time we will have only the blocks used by active process within that Physical Address and this swapping it is what is so called paging or lazy-swapping
- One extra thin , is that a single TTB may not enough as the block size may get bigger when using small TTB and using Big TTB to have smaller block will have performance drawback when walking big TLB to fetch for single entry , one solution was by creating multi level translation stages, so we will have multiple translation tables and each entry of first stage translation table will point to different second level translation table and so on, in ARM it can go up to 3 translation stages with block size of 4 kb
One big advantage as well of using MMU and Virtual Address is making life easy to implement Virtualization using real Hypervisor or Hypervisor type 1by adding extra Addressing mapping stage of virtual address which will be mapped to what is so called IPA (intermediate Physical Address0) which is managed by the hypervisor but this is deep topic can be covered in another post.
