Introduction
The growing popularity of DC systems is largely driven by the proliferation of renewable energy sources, particularly wind and solar, as alternatives to fossil fuel sources. DC systems are not only more economical for long-distance transmission but also offer flexible control, making the integration of renewable energies much easier. Applications of DC systems include high voltage transmission (HVDC), microgrids, data centers, electric aircraft, and shipboard power systems.
However, widespread adoption of DC systems presents some challenges. For the past few decades, power system protection has relied mainly on instrument transformers, communication networks, circuit breakers, and relays. Established standards guide manufacturers in producing protective devices for AC systems, but such standards are still underdeveloped for DC systems. The protection standards for DC systems are immature and a work in progress. It’s crucial to understand that fault behavior in DC systems is fundamentally different, so the protection philosophies for AC and DC systems cannot be interchangeably applied. Consequently, significant research has focused on understanding the characteristics of DC faults.
This article will demonstrate how to perform fault analysis in a DC system. There are two parts to this topic:
- Part 1 covers the process of constructing the model of DC power system under fault condition;
- Part 2 walks you through the necessary steps to run the simulation.
The analytical approach, written in Part 1, involves a set of mathematical equations that explain fault behavior. For the simulation, we will model a simple DC circuit that closely resembles a real-life system, including power converters, control loops, measurement points, and simplified equivalent transmission lines. As the model is built, we will simulate a fault event and analyze the results. Ideally, the analytical and simulation results should match.
Modeling of Simplified DC System Under Fault Condition
Fig. 1 above shows a two-level, voltage-sourced converter (VSC)-based DC system under short circuit condition, where the fault happens at the middle section of transmission line. The DC voltage level of the converter is maintained by the capacitor, denoted as Cdc. To the left of the converter station is AC side, whereas the DC side is on the right.
As a result of fault, the DC side can be represented by an equivalent circuit as shown in Fig. 2. Ldc and Rdc are the lumped parameters of the sectional line, where the fault current loop (if) passes through. The fault penetrates the transmission line, creating a short circuit from upper section (positive) to lower section (negative) through a fault resistance (Rf). The current source represents the current injected from the AC side.
The fault event can be broken down into three stages [1, 2]:
- Stage 1: Capacitor discharge
The DC capacitor responds to the fault by discharging, injecting large amount of current to the fault point. In this stage, the equivalent circuit can be interpreted like a RLC circuit, as shown in Fig. 3.
- Stage 2: Freewheeling diode
As the DC capacitor is fully discharged, the DC voltage declines to zero. Then, the current begins to circulate in the three-phase legs of the freewheeling diode, as the corresponding IGBTs are already blocked (see Fig. 1).
- Stage 3: AC-side current infeed
The AC sources contributes to the overall fault current in this stage. The fault current reaches quasi-steady state until the fault is effectively isolated.
As the capacitor discharge dominates large portion of current, the following analysis will be just dedicated to Stage 1.
Firstly, in the RLC circuit, we have the following current equation:
The short circuit has an impact on the voltage across the DC capacitor. The voltage experiences a sharp decline, for which the behavior can be explained as such:
We obtain the current discharge from the DC capacitor:
Using Eqns. 1–3, the following differential equation can be derived,
Eqn. 4 is a second-order homogeneous ODE. Thus, we can rewrite it to general form:
The solution to this type of ODE has two parts: complementary function (CF) and particular integral (PI), shown in Eqn. 6. Because y(t)=0, the second term on the RHS can be eliminated, leaving only the CF part.
CF of Eqn. 6 is determined by solving the auxiliary equation which is given as:
We obtain the final solution by determining the roots of Eqn. 7, which look like the following:
We introduce new parameters to make Eqn. 8 look cleaner:
The roots depend on the constants inside the square root. Suppose we have the condition below, the roots will be in the complex form.
This is known as under-damped condition. It results in the worst case of short circuit. Because the fault resistance is very low, the fault current can rise to a dangerously high level.
Eqn. 9 is now modified to:
With the complex roots, the general solution of the ODE is given by:
The coefficients A and B in Eqn. 12 are determined by putting the initial conditions (V0 and I0) into the equation. The full derivation will be skipped (refer to [3]), and we finally arrive at the solution of fault current:
We can understand the physical meaning of fault current by examining the function in Eqn. 13. The exponential term significantly impacts the fault current, with its time constant (delta) being highly dependent on the fault resistance. Higher fault resistance results in a larger delta, meaning the fault current takes longer to reach its peak.
The sinusoidal term indicates that the fault current exhibits oscillatory behavior at frequency w1. Two main factors influence the peak fault current: fault resistance and fault location. Lower fault resistance leads to higher current. Additionally, as the fault point gets closer to the DC capacitor, the lumped parameters of the transmission line (Rdc and Ldc) decrease, resulting in higher fault current.
It is important to reiterate that this equation is only valid for Stage 1 of a DC fault. Within 1–2 milliseconds, the fault current will rise to its peak [2]. Shortly after that, Stage 2 will kick in, followed by Stage 3. Throughout the entire fault event, the fault current remains above zero. This presents a challenge for DC system in the conventional protection sense. AC circuit breakers rely on the zero-crossing of AC fault currents to safely isolate faults. However, since DC fault currents lack zero-crossing, an innovative approach is needed to extinguish the high-current arc when opening the circuit breaker [4].
Now, we attempt to find out the solution of DC voltage across the capacitor. It is represented by the equation below:
By putting Eqn.1 into Eqn. 14, we obtain:
Using Eqn. 12, vdc can be modified to:
We perform the integration, resulting in the general solution given by:
Similarly, we use the initial conditions to derive the values of A and B. The final solution of DC voltage is established:
This is the fault behavior for underdamped condition. For simplicity, overdamped and critically damped conditions are out of scope in this article, but the in-depth analysis can be found in [3].
To Be Continued
Part 1 of the fault analysis in DC power system has been covered in this article. The modeling, grounded in mathematical equations, provides a clear framework for anticipating fault behaviors, particularly short circuit in DC line. It is evident that fault resistance and location are the important factors that influence the fault current. Due to different behavior of DC fault, the conventional AC circuit breaker will not work effectively.
In Part 2, you will learn more about fault simulation, which offers a practical means to visualize and test these behaviors in a controlled environment.
References
[1] J. Yang, J. E. Fletcher and J. O’Reilly, “Short-Circuit and Ground Fault Analyses and Location in VSC-Based DC Network Cables,” in IEEE Transactions on Industrial Electronics, vol. 59, no. 10, pp. 3827–3837, Oct. 2012.
[2] C. Li, C. Zhao, J. Xu, Y. Ji, F. Zhang and T. An, “A Pole-to-Pole Short-Circuit Fault Current Calculation Method for DC Grids,” in IEEE Transactions on Power Systems, vol. 32, no. 6, pp. 4943–4953, Nov. 2017.
[3] A. Ukil, Y. M. Yeap and K. Satpathi, "Faults in DC Networks," in Fault Analysis and Protection System Design for DC Grids, Springer, Singapore, 2020.
[4] M. K. Bucher and C. M. Franck, “Fault Current Interruption in Multiterminal HVDC Networks,” in IEEE Transactions on Power Delivery, vol. 31, no. 1, pp. 87–95, Feb. 2016.
