RISC CPU using Verilog
Problem statement
In this project, our primary objective was to design a 32-bit RISC processor using Verilog HDL and then simulate it using a test bench and a waveform. Later this model can also be built in an FPGA (Field Programmable Gate Arrays) chip.
About Verilog
Verilog is a Hardware description language (HDL). It is used to describe a digital system like a network switch, a memory, or a microprocessor. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.
Verilog codes are written in different parts called ‘modules’. Depending on the needs of a design, the internals of each module can be defined at three levels of abstraction. These three levels are:
1. Behavioural or Algorithmic level
It is the highest level of abstraction in Verilog programming. In this type of abstraction designer only needs to know the algorithm of the circuit and does not need to know the gate-level design.
2. Dataflow level
A Dataflow model is a diagrammatic representation of the flow and exchange of information within a system. Dataflow modeling provides the means of describing combinational circuits by their functions rather than by gate structure.
3. Structural level or Gate level
It is the lowest level of abstraction in the Verilog. At this level, the modules are implemented using the primary logic gates and their interconnections. This type of abstraction is a closer representation of the physical implementation.
What is a RISC Processor?
The acronym RISC stands for Reduced Instruction Set Computer, as the name suggests it is a type of microprocessor architecture that uses a small, simple, and highly optimized set of instructions. The RISC architecture is fast, and the chips required for the manufacture of RISC are also less expensive compared to the CISC (Complex Instruction Set Computer) architecture.
● The instruction set contains relatively simple and basic instructions from which more complex instructions can be produced.
● RISC processors make use of the registers to pass arguments and to hold local variables. In general, there are 32 or more registers in the RISC.
● Pipelining technique of RISC executes multiple parts or stages of instructions simultaneously such that every instruction on the CPU is optimized. Hence, RISC has only one cycle for execution time.
● Using RISC, allows the execution time to be minimized, whilst increasing the speed of the overall operation, maximizing efficiency.
● RISC processor is designed with five stages of pipelining:-
○ Instruction Fetch Stage
○ Instruction Decode Stage
○ Execution Stage
○ Memory Access Stage
○ Write Back Stage
Instruction Types
The MIPS32 Instruction Subset Being Considered
● Load and Store Instructions
LW R2, 124 (R8) // R2 = Mem[R8+124]
SW R5, -10(R25) // Mem[R25–10] = R5
● Arithmetic and Logic Instructions (only register operands)
ADD R1, R2, R3 // R1 = R2 + R3
ADD R1, R2, R0 // R1 = R2 + 0
SUB R12, R10, R8 // R12 = R10 — R8
AND R20, R1, R5 // R20 = R1 & R5
OR R11, R5, R6 // R11 = R5 | R6
MUL R5, R6, R7 // R5 = R6 * R7
SLT R5, R11, R12 // If R11 < R12, R5=1; else R5=O
● Arithmetic and Logic Instructions (immediate operand)
ADDI R1, R2, 25 // R1 = R2 + 25
SUBI R5, R1, 150 // R5 = R1–150
SLTI R2, R10, 10 // If R10<10 , R2=1; else R2=0
● Branch Instructions
BEQZ R1, Loop // Branch to Loop if R1=0
BNEQZ R5, Label // Branch to Label if R5 !=0
● Jump Instructions
J Loop // Branch to Loop unconditionally
● Miscellaneous Instructions
HLT // Halt execution
Instruction Cycle
MIPS32 Instruction Cycle
We divide the instruction execution cycle into five steps:
a) IF: Instruction Fetch
b) ID: Instruction Decode / Register Fetch
c) EX: Execution/ Effective Address Calculation
d) MEM: Memory Access/ Branch Completion
e) WB: Register Write-back
Clock Cycles
Model Diagram
Verification using test bench
The verification of the HDL code can be done in two ways i.e Test Bench and Hardware. In our project, we have done the verification by simulating the model with the help of a test bench.
We used the software called ‘Xilinx’ for writing the behavioral model of the Verilog code and then simulated it using the ISE Simulator (ISim) of the same software. The simulation waveform shows different stages of the code like instruction fetch stage, decode stage, etc.
The two test benches are written to test the functionality of the ALU(Arithmetic and Logic Unit) of the RISC processor.
1.This test bench is written to add three numbers by storing them in the processor registers namely R1, R2, and R3.
2.The Second test bench is written to find the factorial of a given number. First, the number is stored in a particular memory location and then its factorial is calculated by applying the basic mathematical operations to different registers.
