Chiplets: Opportunities and Challenges for the Semiconductor Industry
By Joseph Fitzgerald, Christopher Richard, Jan Hinnerk Mohr, Changwook Kim, and Sonali Chopra
“Chiplets” are an increasingly popular design approach upending traditional development, manufacturing, and supply chain processes across the semiconductor industry. They promise a new pathway for companies to keep pace with Moore’s Law, reduce development risk, and more rapidly spawn customer-centric or application-specific silicon solutions. Chiplets, however, introduce a host of operational challenges for individual companies and the industry as a whole as the processes to design, validate, test, and coordinate large-scale manufacturing of chiplet-based designs is inherently more complex. Significant process and value chain re-engineering is ultimately required across business functions and supply chain networks as chiplet-based products proliferate across the industry. Success in harnessing this technology inflection will come to those who can operationally adapt to the new complexities ahead of everyone else or stimulate ecosystems dedicated to chiplet-based designs.
Keeping Up with Moore’s Law
For decades, Gordon Moore’s Law — that the number of transistors on a computer chip will double roughly every two years while the cost is cut in half — has been the observed rate of progress in the semiconductor industry. While the industry has historically kept up with Moore’s Law, it is increasingly clear that the rate of progress is slowing down and new approaches are required. Scaling has largely been exploited for decades to increase performance and lower costs, but now fab capital expenditure costs are outpacing the cost reductions achieved from scaling.¹ At the same time, reticle and die sizes are increasing with many advanced devices approaching their maximum size limits (858mm²)² making die more susceptible to defect density at advanced process nodes.
In a stroke of foresight, in the same paper Gordon Moore forecasted his eponymous law, he also predicted it might be more economical and efficient to create devices from smaller building blocks of functionality and combine them in a package. As the industry advances, transistors on monolithic chips can only get so small.
“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” — Gordon Moore, 1965
Chiplets provide a path through this conundrum, as they enable the semiconductor industry to continue the performance and cost trajectory that has been established by Moore’s Law by exploiting dimensions above and beyond transistor scaling.
Chiplets are small modular pieces of functional circuit blocks that can be combined with other chiplets using high speed interconnects to constitute a heterogenous integrated circuit such as advanced System-in-Package (SiP). The proliferation of applications requiring chiplets is evidenced by the 5X increase in multi-die system design starts over the past 5 years as observed by a leading EDA company.³ Advanced packaging innovations such as embedded multi-die interconnect bridges (EMIB), fan-out, and 2.5D/3D stacking technologies coupled with growth in server, AI, edge computing, networking & telco equipment, and automotive sectors is driving further demand for chiplets. Chiplet architectures provide the next step in the performance evolution of computing hardware.
Accelerating Chiplet forecasts
Advanced packaging represents 44% of the total semiconductor packaging market and $38B in value, yet only 6.5% of the total semiconductor market value in 2021. Looking forward however, advanced packaging is expected to grow at a 9.6% CAGR compared to a 3.1% CAGR for the overall semiconductor market.⁴ These outsized growth projections are underpinned by the benefits of chiplet-based designs, such as:
· Increased yield: Chiplets are less prone to manufacturing defects due to smaller die size and better wafer utilization at the edges thereby increasing the number of known good die available.
· Less over-specification and/or better fit to purpose: Chiplets reduce costs by enabling mixing and matching of dies from leading and mature nodes.
· Improved performance: Chiplets are optimized for specific tasks, bringing about performance improvements above and beyond traditional processing gains. For example, integrated photonics in a multi-die package have been shown to provide 20 times the bandwidth density at half the cost and power consumption.
· Increased chip area: Maximum size of a chip is typically limited by the reticle size. Chiplets bypass this limit by reducing die sizes relative to monolithic designs.
· Less power consumption: Chiplets also reduce power requirements by shortening interconnection distance between chips and decreasing power lost through data transfer.
· More flexible product development: Modularity allows nimbler adjustments to their product portfolios and re-use of existing designs for new use cases. It also de-risks sophisticated SoC development by shortening the design time and enabling greater confidence in hitting application specs. In other words, the increased modularity makes companies more adept at meeting specific requirements of applications.
Taken together, the accelerated pace of the advanced packaging market represents an enormous opportunity for companies that can move nimbly in adopting advanced packaging and chiplets.
Opportunities and challenges for chiplet-based semiconductor solutions
The flexibility offered by modular plug-and-play chiplets is creating whitespace opportunities for small and large players alike. Smaller players and startups, such as those developing smart substrates or high-performance custom CPUs, are finding new market entry points while incumbent players are investing billions of dollars in advanced packaging capex.
To take advantage of chiplets, companies across the value chain must re-engineer their operations as decades-old, tried-and-true semiconductor operational processes need to adapt to a new reality. While chiplets offer many potential benefits, they also present significant operating challenges due to the heterogeneity involved in the manufacturing process, materials requirements, design and validation complexity, and — not the least — supply chain management.
Companies can expect challenges across nine functional areas:
1. Product Development: Companies must re-engineer their product lifecycle management practices to reduce the time from product definition to manufacturing ramp without increasing headcount and cost. To manage the number of permutations, combinations, and specifications, enabled by chiplets, product development teams need new tools and ways of working to collaborate across engineering functions, supply chain and fab/OSAT partners. Managing concurrent engineering with an explosion of data (i.e. Bill of Materials, Simulations, Design Files) is critical. Investments in automation of workflows and data management is essential to maintain required cost and headcount targets. At the same time, existing cost models must evolve to incorporate chiplet choices in design and options when choosing manufacturing partners.
2. Engineering: Chiplets enable IP blocks from different vendors to be assembled into one packaged product. To combine functional blocks from different vendors, standardized interfaces are required. There are multiple industry standards for system designers to choose from while designing die to die interconnects (e.g., Intel’s AIB and MDIO, TSMC’s LIPINCON). Not to mention, there are current pushes to create open-source solutions (e.g., UCIe, BoW). Solutions like UCIe (Universal Chiplet Interconnect Express) are being developed by leading industry players to accelerate advancement of chiplet architecture. At the same time, chiplets will necessitate new system pathfinding approaches to optimize manufacturing processes. Updated electronic design automation (EDA) and simulation tools will be required to model new chiplet designs and manufacturing choices.
3. Validation and Testing: In the absence of fully defined industry standards there will be continuous integration challenges with chiplets to drive required yield. Integrating system and product roadmaps for multiple generations will be critical to navigating these challenges. The conventional method of qualification applied by IDMs and OSATs to validate each chiplet across its operating specs individually and in the final package for all potential combinations of chiplets will demand cumulatively higher validation and qualification resources as chiplets must be tested for observability, testability, debuggability, reliability, and vulnerability. Companies must practice a ‘shift left’ strategy and test early and often to identify issues as early as possible in the development process. Incremental software modules to build and test package architecture and design will need to be developed.
4. Marketing and sales: Building customized solutions for customers will require tight coordination between marketing, engineering, and production teams, as well as product data management tools with customizable features. Given the complexity involved, customization of products needs to consider the tradeoffs between cost — time, effort, money — and potential revenue. Long-term, companies can imagine a world where they have a catalogue of chiplet options for customers to choose from in the same way that PCs were once configured to order — something that has not been practical in the semiconductor industry to date.
5. Planning process: Managing a supply chain to enable 5, 10, 20, 40… chiplet types, plus materials to come together across potentially multiple global locations is a significant leap from industry norms today. With chiplet-based designs in relatively low volume today companies can manage with workarounds. However, once volume increases, the ensuing complexity requires planning automation and advanced forms of forecasting. Supply planning tools (i.e., Advanced Planning Systems) will need re-engineering to drive production signals across a greater number of sites and react to changes in the plan. Mid to long term planning will require companies to better forecast demand by feature and drive wafer starts to generate sufficient, but not excessive chiplet die banks. Planning must integrate with testing to enable a shift left strategy and align compatible chiplets to maximize production and utilization of chiplets produced.
6. Procurement: For IDMs, the set of chiplets will most likely be sourced both from internal manufacturing and from multiple external suppliers to accommodate heterogenous integration. This will require companies to adapt their existing procurement processes and procedures. For example, chiplet die bank safety stocks will need to be larger to achieve the same service level as a monolithic chip die bank. Additionally, chiplets will generate a plethora of potential Bills of Materials (BoMs) given the different permutations of silicon required. Engineering and operations leaders will need to revise their current operating model to ensure that various chiplet die banks meet desired performance grades of products. All of this will be further complicated if some chiplets are externally procured while others are internally fabricated.
7. Manufacturing and quality control: There will be new and more manufacturing steps to integrate chiplets on a substrate. Companies can expect increased cycle times and a more complex end-to-end MPS (Master Production Schedule) generation due to the additional steps and chiplet combinations. Companies will need a more sophisticated planning optimizer to achieve their expected OEE (overall equipment effectiveness), throughput, on time delivery, and cost goals. Moreover, companies must adjust continue adherence to the “known good die” standard. This standard requires that a given die or unpackaged IC has the same quality and reliability as an equivalent packaged device and can be shipped directly to customers for assembly in their products. To meet this standard, companies will likely need to expand their guard bands (allowances for errors while still maintaining overall functionality) to ensure quality outcomes amidst the natural variation that will occur in production. These additional steps require new capabilities for companies pursuing heterogeneous integration.
8. Governance: Heterogeneous integration will shift responsibilities across the semiconductor value chain, requiring businesses to reinvent how they work. For example, IDMs and fabless companies now provide integrated solutions to ODMs and OEMs, thus moving responsibility of integration up the value chain. Semiconductor players using chiplet architectures will need to devise solutions to tackle complexities involved in building more advanced cost models, accounting for quality issues, and integrating packaging roadmaps with system roadmaps.
9. Cost accounting and finance: Calculating standard and actual costs and margins for finished goods will increase in difficulty as product BOMs become more complex. Should-cost models will need to account for multiple dice manufactured on multiple processes and more difficult to forecast yields. Companies will need to revisit how they collect cost data for chiplet integration steps done internally and externally plus manage yield and scrap impact when products fail yet the failure mode is related to system integration faults. While new to mainstream semiconductor manufacturing, these methods are not new to the high-tech industry. Semiconductor companies can learn these methods from their customers who design and manufacturer boards and systems with tight tolerances.
How can companies get started? Partner with BCG’s semiconductor operations practice and BCG X to re-engineer operations and build supporting capabilities for business processes to overcome these challenges.
At the intersection of technology and operations, BCG’s Tech Ops practice enables our clients to transform their businesses to win in the 21st century. We have a global network of semiconductor industry experts situated in key geographies where semiconductor companies are concentrated. We served approximately 400 clients across the value chain over the past 10 years, including 250 in the past 5 years. Our operations practice provides functional expertise to support broadscale transformations to support client’s goals and ambitions. BCG’s operations practice supports sophisticated tools and techniques, in addition to a large world class team that includes 200 MDPs, 700 operations professionals globally, in addition to 11 dedicated Operations centers: BCG’s extensive work with semiconductor industry has enabled partnerships including with leading software solution packages. These alliances support dissemination of best practices, foster discussions around industry challenges and opportunities, and improve the value impact of our work.
BCG’s Tech Ops practice also works in collaboration with BCG X, BCG’s technical building arm that that brings together advanced technical knowledge and ambitious entrepreneurship to help organizations launch their next big bets and enable innovation at scale. BCG X is comprised of nearly 3000 technologists, scientists, programmers, engineers, and human-centered designers with expertise in AI, deep tech, digital growth, sustainability, and more. Through comprehensive partnerships with BCG X, our clients rapidly launch new solutions that are ready to run from day one.
ACKNOWLEDGEMENTS
The authors would like to thank Shreya Dwarakanath, Omar Aboulezz, Kailash Bhat, Sagar Mukala, Abhishek Saraf, and Miriam Rollock for their help in conducting research for this article.
REFERENCES
- Statista. “Capital expenditure in the global semiconductor industry from 2000 to 2022” sources (Gartner; IC insights). https://www.statista.com/statistics/864897/worldwide-capital-spending-in-the-semiconductor-industry/
- Mask / Reticle — WikiChip. (n.d.). https://en.wikichip.org/wiki/mask#Reticle_limit
- Posner, M., (2023, January 25). Annual Update on Interfaces [Conference presentation]. Chiplet Summit, San Jose, CA, United States. https://chipletsummit.com/
- Yole Group. (2022). Status of the Advanced Packaging Industry (Market and Technology Report 2022). https://www.yolegroup.com/product/report/status-of-the-advanced-packaging-industry-2022/
