Researchers Find A Way To Make Smaller Chips

In other news, Moore’s law still stands.

Saturation leads to stagnation, but sometimes it can also be an incentive to find new ways to progress.

Take the example of chips — the silicon heart of every electrical device you will ever use — they are one of the first few bastions of Moore’s Law.

Continuous progress in technology and materials has made chipsets (and consequently, computers) increasingly smaller, charting a trajectory from a city-sized Eniac to a diary-size Macbook. Yet, as jubilant as today’s inventors may be, they continue to face an immutable concern — “What next?”. More like “How next?

Their conundrum relates to Moore’s Law, and his estimation of the progress rate towards the number of transistors that can be shoehorned into a specific size of silica, given technology prevalent at the time. Per Moore’s Law, with changes in the given materials and technology of the day the number of components on a circuit can at best, double every. And that, is not a restriction that inventors can wish away.

Moore’s law has governed the chip industry or decades, setting the precedent for further development in the way the chips are made.

But enhancing the computing size in increasingly smaller sized chips, means that technological progress would come to a halt, unless new ways of increasing computing size are found. But there’s a limit to that too — an increase in wiring density also leads to an increase in the heat emitted from the chips.

Now, researchers from the Massachusetts Institute of Technology and the College Of Chicago have come up with a novel solution that can extend the possible shrinking in the size of chips, and provide a shot in the arm to circuit makers.

I suggest you grab your cup of coffee, or latte, or a tall glass of fresh lime before I proceed. It’s going to an interesting read, for a hungry mind. I’ll wait.

Okay, here we go now.

The answer revolves around the principle of self-assembly of the wiring on chips.

Existing technologies use an electron beam to etch patterns on the chip.This process is quite time-consuming and mechanical. The small transistors are forged using a small-wavelength electron beam.The wavelength can be reduced by using Extreme Ultra-Violet (EUV) lithography, but that process is quite expensive and challenging.

With the new process, a mix of two polymers is laid down on the chips, where they form patterns voluntarily. The electronic etching part is same as before. But there’s a twist.

These polymers are made up of chain-like molecules, in which the end-to-end connection is done by two different polymers.The first polymer is heated till it vaporises , then it is allowed to condense on a cooler surface. Then a coating of protective polymer is added on those two existing layers, which allow them to form a dense vertically oriented pattern.

Unlike the existing chip patterns, this pattern is a significantly condensed one, putting four wires into the space of one! This is similar to the process of 3-D Transistor manufacture. And this technology can be used in 7-nm electron beam setup too, instead of a 10-nm setup that is currently used.

The solution was published in the journal Nature Nanotechnology, in a paper by postdoctoral researcher, Do Han Kim, graduate student Priya Moni and Professor Karen Gleason — all at MIT, and by postdoctoral researcher, Hyo Seon Suh, Professor Paul Nealey, and three others at the University of Chicago and Argonne National Laboratory.

The paper claimed that the new process would be cost effective too, for the materials that are added are already used in the chip industry and the process is nearly identical to the existing one.

That said, it’s still going a long time before the process is proven and adopted substantially by the industry. Change does take time, especially in something as widespread and exacting as chip-making.

The paper promises chip speeds that are unheard of at the current time. The best part? Even if these solutions are incorporated, Moore’s law would still stand!

Originally published at Chip-Monks.