New Block Diagram; Internet is bad

Derek Payne
Sep 2, 2018 · 2 min read

By request, I have updated the block diagram to be readable.

Handheld FRA, revision 2. Now readable. A few tweaks are included, and a few bits have been discarded. Isolation on the ADC was a bad idea, so it’s been removed. However, isolating the user from a host PC is a good idea, and takes very little space by comparison. I think this also means that galvanic isolation is required on the input supply to the battery, but most supplies include this. I have located a convenient DSP/MCU combination which meets the needs of this project, which will be the subject of many future posts. Inputs are now demuxed and probably scanned for simplicity. A few “Offset DAC + Amp” blocks have been added, but these should not necessarily be treated as DACs at the moment; it’s possible that a simpler solution exists for this problem. I expect that the DC/DC blocks will change as I become more aware of the power rail requirements. An SD card has been added, for dedicated non-volatile storage when a USB port is unavailable. Non-volatile ROM may be necessary as well, but at this time it is still uncertain. The clock tree and battery management ICs have also been linked to the DSP, since clock tuning and battery charge/health monitoring are no doubt required. Until the reconstruction filter architecture is more fully thought out, its power rails will be left undetermined. Finally, the internal on-board self-calibration will be left to future consideration. After all, it’s both possible and easy to just connect the instrument output directly to its input.

I have spent some time investigating components which could meet the project requirements, and I have likely candidates for the ADC, the DDS, and the DSP/MCU which can work together harmoniously. I would love to provide an update on my decision-making process for these components.

However…

The state of my internet. Modem restarted yesterday. Note that in only 24 hours, the number of correctable errors has grown so much that the signed 32-bit counters have overflowed on several channels!

DOCSIS standards state that an SNR of 37 dB is considered the minimum normal signal quality, and 33 dB is considered the minimum acceptable limit. All of my channels are 3–7 dB below the minimum acceptable limits, with five completely failing to lock. Consequently, it took about five minutes for Medium to upload each image in this post. Clearly, there is a problem.

The fix will take a few days. When I return, I will discuss my choices for the ADC, the DDS, and the DSP/MCU.

Until then, here’s a preview:

ADC: ADS4222 (Texas Instruments)
DDS: AD9913 (Analog Devices)
DSP: OMAP-L132 (Texas Instruments)

Circuit Design for Fun and (no) Profit

Follow along as I step through the hardware design process for various electronic equipment. Concept definition, component selection, schematic, layout, embedded programming, prototype evaluation, revisions, and final release. Everything is open-source.

Derek Payne

Written by

Applications Engineer for a Semiconductor Company. I design stuff for fun. Everything I make is open-source.

Circuit Design for Fun and (no) Profit

Follow along as I step through the hardware design process for various electronic equipment. Concept definition, component selection, schematic, layout, embedded programming, prototype evaluation, revisions, and final release. Everything is open-source.

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