CPU Architecture Made Simpler!
First of all you need to know what is CPU? It is not what you were taught at school there is so much to it. For this you have to get a proper idea for the architecture of the CPU and its components , here we are going to talk about Von Neumann architecture.
Von Neumann architecture
There are two types of computers: (a)Fixed Program Computers are those that have limited number of specific functions and can’t be reprogrammed. Ex, calculator.(b)Stored Program Computers, these are those that can be programmed to perform multiple task and have a memory unit attached to it. The modern concept of stored program computers was given by John Von Neumann . In this architecture programs and data are stored in a separate storage unit called memories and are treated the same.
The basic structure of the computer can be is,
(a)Input/Output device: You know about this right the elementary stuff! Input device keyboard,mouse etc because they take input from the user ,whereas Output devices printer , speaker etc are which provide certain output to the user.
(b)Buses: These are basically the channels of communication between various components of the computer and the memory .The purpose of buses is to reduce the number of “pathways” needed for communication between the components, by carrying out all communications over a single data channel. There are three types of buses:
# Data Bus- It basically carries data between the memory , I/O devices components and the processor
# Address Bus- It is used to specify a physical address to be referred in the memory . During execution of program, it helps the processor or DMA(explained later) to read and write data in the memory by referring to the address location to be accessed basically helping the CPU in communicating with various components.For example , a system with 16 bit address bus can address 2¹⁶ memory locations.
# Control Bus- These carries commands from the CPU and returns status signals from the device.For example,which appropriate line (read or write)to be activated for a particular data to be read or written in memory
(c)Control & Processing Unit- Okay,here comes the brain of your computer without this it is just costly paper weight. CPU is the just combination of ,
(i) Control Unit , It directs the operation of the other units by providing timing and control signal and directs the flow of data between the CPU and the other devices. It tells the computer’s memory, arithmetic and logic unit and input and output devices how to respond to the instructions that have been sent to the processor.
(ii)Arithmetic Logical Unit(ALU), is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers.
A ,B and X are three parallel data buses . Each data bus is a group of signals that conveys one binary integer number. A and B takes input and depending on O (opcode) i.e, addition,multiplication etc X gets the output
Sets of basic operations are hardwired onto the CPU known as instruction set. These basic operations are represented by particular combinations of bits,called opcode (Machine level language); while executing instructions in a machine language program, the CPU decides which operation to perform by “decoding” the opcode.
(iii)Registers , these are a type of computer memory used to quickly accept, store, and transfer data and instructions that are being used immediately by the CPU. It is preferred for its speed,it can be easily accessed almost at the speed of the processor,rather than getting data from the memory it is way more fast.But the disadvantage is that there are limited numbers of registers and they are much costlier.
Some main registers:
# Accumulator- The accumulator is a register in which intermediate arithmetic and logic results are stored. Accessing the main memory is much slower to access so, fast memory like accumulator is preferred.
# Program Counter (PC)- PC provide the temporary housing for the next instruction that is to be executed in a string of instructions. As one instruction is retrieved and implemented, the program counter queues up the next instruction in the string, effectively minimizing delays in the execution of steps necessary to complete a task. By always pointing at the next instruction, the process is kept moving forward efficiently.
# Memory Address Register (MAR)- The Memory Address Register is the CPU register that either stores the memory address from which data will be fetched from the CPU, or the address to which data will be sent and stored along with control signal to memory. In other words, MAR holds the memory location of data that needs to be accessed.
# Memory Data Register (MDR)- The register MDR is used to store the data which has been sent from the memory. The data is then stored in MDR will be sent to IR where it will be decoded such that the processing of data occurs after that in processor.
# Current Instruction Register (CIR)- This holds the instruction currently being executed or decoded. It generally holds each instruction to be executed while it is decoded, prepared and ultimately executed, which can take several steps.
# Instruction Buffer Register (IBR)- IBR is a temporary register where the opcode of the currently fetched instruction is stored.
# Memory Buffer Register (MBR)- MBR is a temporary register where the contents of the last memory fetch is stored.
#General Purpose Registers(GPRs)- General purpose registers (R0….Rn) can store both data and addresses, i.e., they are combined data/address registers. They are used for passing parameters to functions, storing return values, and intermediate values during computations.
#Stack Pointer(SP)- A stack pointer purpose is to keep track of a call stack stores the address of the last program request in a stack i.e, the top of the stack
#Index Register(xR)- xR holds an index number that is relative to the address part of the instruction. The actual address of operand is the sum of the constant and the content of xR
#Base Register(Br)- Base Register holds a base address and the direct address field of instruction gives a displacement relative to this base address.
Von Neumann bottleneck
The main drawback of Von Neumann architecture is that bus is shared which although enhance performance , but the limited throughput (data transfer rate) between the central processing unit (CPU) and memory compared to the amount of memory, i.e, we cannot get away from the fact that instructions can only be done one at a time and can only be carried out sequentially whish leads to the Von Neumann bottleneck condition.
Because the single bus can only limited to access one of the two classes of memory at a particular instance of time, data transfer rate is much lower than the rate at which the CPU usually work. This seriously hampers the processing speed when the CPU is required to perform minimal processing on large chunks of data. The CPU is continually forced to wait for the data low transfer rate memory. The bottleneck has become more of a problem, since CPU speed and memory size have increased with every new generation of CPU much faster than the transfer rate between them.
