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Adjustable Analog Filter


Figure 1: Analog Interface with One Tunable Filter

The complete design file is available here. It was programmed in the GreenPAK Designer software (a part of Go Configure Software Hub) that is a free-to-use GUI-based program aimed to create circuit designs.

1. System Overview

This filter is implemented with two resistors, two capacitors, and an operational amplifier. Two resistors in this circuit are replaced with the SLG47004 Digital Rheostats, and one of the SLG47004 operational amplifiers is used as an active element.

Figure 2: Sallen-Key Filter Based on the SLG47004

By adjusting two Digital Rheostats the cutoff frequency and the approximation method of this active filter can be changed. The Butterworth approximation method was used in this article. The frequency behavior of the Butterworth filter is maximally flat in the magnitude response in the passband. The rate of attenuation in the transition band is better than the Bessel filter, though not as good as the Chebyshev filter. There is no ringing in the stopband. The step response of the Butterworth filter has some overshoot and ringing in the time domain, though this is comparatively less than the Chebyshev filter.

The equation for the low-pass filter configuration on Figure 2 is:

where K = 1;

This formula can be used to calculate the appropriate resistance and capacitance. Alternatively, it is possible to determine the capacitors and resistors values using filter design tools [5].

The capacitor values in the filter circuit are kept constant while the resistive elements are adjusted. For this project, capacitor valuse chosen are: C1 = 270 pF and C2 = 27 pF.

The SLG47004 contains two 10-bit Digital Rheostats. The full resistance for both Digital Rheostats is 100 kΩ. The range of digital code that corresponds to the rheostat resistance is from 0 to 1023 (1024 taps). Code 0 corresponds to the minimum resistance between the RHx_A and RHx_B terminals. As the code value increases, the resistance between the RHx_A and RHx_B terminals monotonically increases. Consequently, when the code value decreases, the resistance between the RH0_A and RH0_B terminals decreases as well. The voltage on any rheostat pin can be in the range from AGND to VDDA, and can be dynamically changed during operation.

The values calculated for this filter design are summarized in Table 1. This table also includes the closest resistance values for RH0 and RH1 along with the digital program code.

Table 1: The Butterworth Filter Design Adjusting the Resistors through a Digital Rheostat

2. Functional Block Architecture

Figure 3: GreenPAK Designer Project

2.1. Setting Rheostat Data

Figure 4: Digital Rheostat 1 Properties

2.2. Changing Rheostat Data

2.2.1. Changing Rheostat Value via I2C

Figure 5: I2C Connection to Change Rheostats Resistance

2.2.2. Changing Rheostat Value via Internal Logic

Figure 6: Internal Logic Block Diagram to Change Rheostats Resistance

A High level signal on the Start (Pin 16) and Reset (Pin 15) pins allows switching between two different frequencies. When the rheostat’s initial value is set to 100 kHz cutoff frequency, the High level signal on Pin16 starts changing this frequency to 1 MHz (Figure 7). The High level signal on Pin15 resets the frequency again to 100 kHz (Figure 8).

Figure 7: Internal Logic for Changing Rheostat Resistance
Figure 8: Rheostat Reloading Unit

To detail this behavior further, for 1 MHz cutoff frequency RH0 resistance is 488 Ω (code 4) and RH1 is 7.910 kΩ (code 80). To change the frequency to 100 kHz the RH0 resistance = 4.395 kΩ (code 44) and RH1 resistance = 78.906 kΩ (code 807). So, for RH0 the digital code value must be increased by 40 and for RH1 by 727. To increase the resistance in the rheostat’s settings “Active level for UP/DOWN” must be set to “Up when High”.

8-bit and 16-bit Counters can be configured to provide the necessary number of clock pulses from the oscillator to the rheostats. 8-bit Counter data must be set to “40” and 16-bit Counter to “727”.

СNTs stop is provided by the internal logic (Figure 7). When “Start Logic” signal goes High, DFFs will trigger on its rising edge. A High level on DFFs outputs will cause a clock signal on LUT0 and LUT2 outputs. After that, Counters values start going down and when they reach “0” a High level will appear at LUT1 and LUT3 inputs respectively. As these LUTs are NAND gates, a High level of signals on their inputs will reset the corresponding flip-flop and will stop counting.

Software simulation results for this internal logic are shown in Figure 9. For hardware testing refer to Figure 10.

Figure 9: Software Simulation of Internal Logic at CNT5 Data = 5
Figure 10: Hardware Testing Waveforms for Internal Logic at CNT5 Data = 5

For resetting the cutoff frequency Pin15 works as a Digital Input and is connected to “Reload” input of the rheostats. When Reload signal goes High, the rheostat value stored in the MTP NVM will be loaded into the rheostat (Register and Counter) overwriting any current setting. For the normal rheostat operation “FIFO nReset” input should have a logic High level (Figure 7).

2.3. Macrocells Settings

Table 2: LUTs Settings
Table 3: DFFs Settings
Table 4: PINs Settings
Table 5: OpAmp Settings
Figure 11: I2C Settings
Figure 12: OSC Settings
Figure 13: Digital Rheostat Settings for 1 MHz Cutoff Frequency
Figure 14: Counter Settings

2.4. Software Simulation

Figure 15: Simulated Frequency Response of Filter for Two Cutoff Frequencies

2.5. Hardware Testing

Figure 16: Frequency Response of Prototype Filter for Two Cutoff Frequencies




GreenPAK™ is a broad family of cost effective NVM programmable devices that enable innovators to integrate many system functions into a single custom circuit, and in the process minimize component count, board space, and power consumption.

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