3D Chips— The future of computing!
The tiny, humble, yet the powerhouse of the electronic devices we use, the humble transistors has come a long way since its inception, from a MOSFET with a gate size of 20 micrometers in 1968 to 2 nanometer gate FinFETs under risk production from 2024, the devices have become incredibly small and in the inverse, have become insanely powerful and reliable in terms of its performance and power to output ratio. From using 5 kB of RAM and 32kB of memory for the Apollo 11 mission in 1969, now everything has moved a minimum of Giga and Tera scales for the memory. While the gate size has evolved by manifolds over the years with regard to Moore’s Law which is the observation that the number of transistors in an integrated circuit (IC) doubles about every two years.
While the transistor’s gate size drastically reduced, the architecture of placement of chips has also evolved through the years.
2D System on Chip ( 2D SoC )
Traditional chip design process involves placement of the transistors on the wafer side by side, making the layout in a 2D format.
This method of chip layout in the wafer requires:
1: A lot of space on the wafer, as less components can be placed on the sides as each chip requires its own space, which in turn decreases the chip density for the wafer.
2: Complex electric network layout for the various ICs to perform optimally.
3: Higher time required for data transfer as the memory chip might be located not near to the processor and the memory bus follows a convoluted path which reduces the data transfer rates.
4: Increased bulkiness of the device as the final board will be larger and bulkier.
5: As the number of soldered joints are high and as every single chip might have its own joint, the risk of failure is very high.
6: With less density of chips on a wafer, the cost of manufacturing soars. Considering a single 30 cm diameter wafer can cost around $1000 dollars for a wafer containing sub 150 nm architecture and increases drastically with reduced length of chip architecture.
2.5 D System on Chip ( 2.5 D SoC )
With the following parameters in mind, the manufacturing process moved initially to 2.5D which involved the placement of an interposer. Interposers are wide, extremely fast electrical signal conduits used between wafers in a 2.5D configuration.
2.5 D Chips is just a better optimised version of 2D Chips, the 2D Chips lack the interposers the 2.5 D ICs possess. As interposers just manage power supply and give better thermal stability, With Moore’s law and the laws of physics reducing the possibility of a sub < 2 nm gate IC, it becomes inevitable for the manufacturers to move to a different assembly of ICs where the existing issues can be addressed and fixed.
3D System on Chip ( 3D SoC )
3D SoCs is manufactured with chips stacked over each upto 16 ICs over each, which effectively reduces the area occupied in 2D and 2.5D ICs. By vertically stacking the chips, the advantages are:
1: Better space management as the ICs on the wafer are increased and more ICs can be stacked over the same IC on the same wafer reducing the lateral usage which increases the space on the sides.
2: The stacking process makes way for a less convoluted electric network for a better power supply and the network design becomes easy and has less joints.
3: Data transfer speed increases by manifolds as the distance between the processor and the memory drastically reduces and with the memory buses having a less turbulent path to take, the data transfer speed increases exponentially.
4: With fewer joints, the possibility of failure reduces and in case of any issues, troubleshooting becomes easy.
5: 3D Chips ICs can reach upto a speed of 100 GHz for data transfer within the SoC.
Conclusion :
Intelligent use of space, power in the wafer has proven to be the real game changer, with reduced space, power usage, the chips have conversely become more efficient and more powerful than its predecessors. While 3D stacking is still under experimental usage and not out for commercial usage yet, the initial signs are promising and with AI and Data taking over the reigns, a faster mode for data transfer and processing the data is required and 3D ICs stand synonymous for the same.
