Edge Analytics
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Edge Analytics

Neural Network on the Tip of a Pencil

Mapping 2-Dimensional Algorithms to Hardware with FPGAs

[Left] A GPU is optimal for embarrassingly parallel image-processing algorithms. The video is smooth. [Right] The serial limitations of the CPU result in noticeable delays and poor performance. Source for the videos
[Left] Depiction of how a CPU solves a problem in 1D with serial execution of instructions one at time. [Right] Depiction of how HW accelerators such as GPUs, FPGAs, and ASICs can map computation in 2D with parallel computation in space and over time.

Sleep Tracker: Neural Network on the Tip of a Pencil

We deployed 3-layer feedforward neural networks (left) on an FPGA that is smaller than the tip of a pencil (middle, circled in green) and found in the iCE40 Ultra Wearable Development Platform (right).
High level architecture diagram of our FPGA sleep tracker. On the front end, an STM IMU chip is the data source connected to our FPGA. On the backend, we can connect a host computer to read off data and issue commands to the sleep tracker. We developed our own sampler, featurizer, NN core, and UART core from scratch in SystemVerilog. This allowed us to realize an efficient solution deployable on tiny FPGAs.

The Future of 2D Algorithms on Adaptable Accelerators

Our NN deploy pipeline enables non-FPGA experts to train new models and deploy to FPGAs. The steps of the pipeline include training and exporting a Keras model, using a script to parse the output model into data the FPGA compiler toolchain expects, updating model constants in the top-level FPGA project file, and re-compiling the FPGA bitstream.
Diagram of the top-level test bench for our sleep tracker application. The ability to use Cocotb and Python is a boon for testing, validating, and debugging FPGA designs. The convenience of Python async/await syntax and the ease of mocking subcomponents/importing test data in Python greatly accelerated our work.
A vision for using Rust as CPU <-> FPGA glue, including code generation facilities for common classes of I/O.



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