[press-release] EdgeCortix and PALTEK jointly exhibit at Artificial Intelligence/AI EXPO 2021
Exhibiting the latest EdgeCortix AI processor hardware IP and AI development kit for FPGAs at AI EXPO 2021 in Tokyo.
EdgeCortix Inc. (Headquarters: Shinagawa-ku, Tokyo, CEO: Sakyasingha Dasgupta, hereafter called “EdgeCortix”) will be presenting for 3 days from April 7th (Wednesday) to April 9th (Friday) 2021, at the “5th AI / Artificial Intelligence EXPO [Spring]” to be held at Tokyo Big Sight Aomi exhibition hall. At this event, we will jointly exhibit with PALTEK Corporation (Headquarters: Kohoku-ku, Yokohama, President: Tadahito Takahashi, Securities code: 7587, hereafter called “PALTEK”).
The exhibition will demonstrate a preview of EdgeCortix’s latest hardware IP for FPGA’s, Dynamic Neural Accelerator® DNA-F400 and the MERA™ compiler. The DNA-F400 is a new product in EdgeCortix’s Dynamic Neural Accelerator F-series IP family for low-latency deep neural network (DNN) inference applications on FPGAs. It is specially designed for Xilinx Alveo™ U50 / U50LV Adaptive Accelerator Cards that support HBM. DNA-F400 (7.48 INT8 TOP/s at 300MHz) and its predecessor DNA-F200 (3.7 INT8 TOP/s at 300MHz) are high-performance convolutional neural network (CNN) inference IPs with ultra-low latency and high energy efficiency ideal for high throughput streaming data applications at the edge.
The DNA-F-series IP will be demonstrated together with the MERA™ compiler and software toolkit. This enables deployment of deep neural networks designed with popular machine learning frameworks such as PyTorch and TensorFlow-lite to FPGAs with minimal effort. MERA enables machine learning engineers to optimize and run networks designed for CPUs or GPUs, with INT8 bit quantization out of the box on the DNA IP implemented on Xilinx Alveo or Ultrascale+ MPSoC FPGAs. The compiler automatically identifies which parts of the neural network can be offloaded to the accelerator and automatically offloads new or unknown operators to the host processor. The MERA compiler also comes with a built-in simulator and interpreter. After compilation, customers can use these tools for performance estimation without testing on the hardware as well as to quantify the impact of INT8 bit quantization on network accuracy.
In addition, PALTEK will demonstrate the Alveo U50 AI Starter Kit equipped with EdgeCortix’s inference engine (DNA-F200) in “CERVO Grasta PALTEK FPGA *¹”. This is equipped with the Xilinx Alveo™ U50 Data Center Accelerator Card *² jointly developed with Applied Co., Ltd. (Headquarters: Fukuoka City, Fukuoka Prefecture, Representative Director: Yoshiharu Oka, Securities Code: 3020, hereinafter called “Applied”). The Alveo U50 AI Starter kit is a development kit that allows customers who want to improve real-time performance for AI applications, to migrate from the GPU-based environments at an early stage.
At the exhibition, the organizer and our company will take individual measures against infectious diseases before serving customers. We appreciate your understanding and cooperation with such measures while visiting us. Further information on such preventive measures is provided by the organizers on the AI EXPO website.
Outline of the exhibition
Exhibition name: “5th AI / Artificial Intelligence EXPO [Spring]”
Date and time: April 7, 2021 (Wednesday) to April 9, 2021 (Friday) 10: 30–18: 00
Venue: Tokyo Big Sight Aomi Exhibition Building (1–2–33 Aomi, Koto-ku, Tokyo) Booth : 1–35
Organizer: Reed Exhibitions Japan Co., Ltd.
Exhibition URL: https://www.ai-expo.jp/
Main exhibition contents
EdgeCortix’s latest hardware IP, Dynamic Neural Accelerator® and MERA™ compiler
1: Alveo™ U50 Data Center Accelerator Card *3, Equipped AI Starter Kit (DNA-F200 *³)
2: Alveo™ U50 Data Center Accelerator Card + Latest IP (DNA-F400)
3: Zynq® UltraScale +™ MPSoC ZCU104 Evaluation Kit + DNA-F050 *⁴
Alveo U50 AI Starter Kit
“AI Starter Kit” equipped with EdgeCortix’s AI inference engine on “CERVO Grasta PALTEK FPGA” jointly developed by PALTEK and Applied. Exhibiting solutions that can be processed at high speed by edge servers, such as high-resolution object recognition (with neural networks like YOLOv3, SSD) used in security systems and high-resolution single camera based image depth estimation (with large neural networks like Monodepth).
Explanation of technical terms
* 1. CERVO Grasta PALTEK FPGA
This is a dedicated HPC workstation equipped with a Xilinx Alveo ™ U50 data center accelerator card as standard equipment. It supports all workloads such as computing, machine learning, computing storage, data retrieval / analysis, and provides optimized acceleration capabilities.
For details, please see https://bto.applied.ne.jp/c19-c2207.html.
* 2. Alveo ™ U50 Data Center Accelerator Card
Xilinx accelerator card that demonstrates excellent performance for high-speed processing such as deep neural network inference. For more information, please visit https://japan.xilinx.com/products/boards-and-kits/alveo/u50.html.
* 3. DNA-F200
The DNA-F200 (3.7 INT8 TOP/s at 300MHz) is a product of the EdgeCortix Dynamic Neural Accelerator®︎ dataflow architecture-based IP family for deep neural network (DNN) inference applications on Xilinx Alveo FPGAs.
* 4. DNA-F050
DNA-F050 (0.6 INT8 TOP / s at 300MHz) is a product of the EdgeCortix Dynamic Neural Accelerator®︎ dataflow architecture-based IP family for deep neural network (DNN) inference applications on Xilinx UltraScale +™ MPSoC FPGAs.
*The Xilinx name and Alveo, UltraScale +, Zynq, and other brand names mentioned in this press release are registered trademarks or trademarks of Xilinx in the United States and other countries. All other names belong to their respective owners.
* Dynamic Neural Accelerator® and MERA ™ are registered trademarks or trademarks of EdgeCortix Inc., in Japan and other countries.
About EdgeCortix Inc.
EdgeCortix, Inc. was founded in 2019 with the corporate mission to “bring cloud-level performance to the embedded edge, for low latency, low cost, and energy-efficient deep neural network inference”. The company’s strength is in its unique artificial intelligence processor technology designed with an integrated hardware and software co-design approach. EdgeCortix has raised a total investment of 525 Million Yen till date from investors in Japan, Singapore and USA. It has a proven track record of achievements with existing partnerships with multiple companies in the electronic manufacturing industry. Taking a software centric approach to AI hardware IP creation, their Dynamic Neural Accelerator® IP core and MERA™ compiler is designed to work with little effort across custom ASICs and FPGAs.
For more information about Edgecortix, please visit https://www.edgecortix.com/.
About PALTEK Corporation
Since its founding in 1982, PALTEK has been selling semiconductor products in Japan and overseas to electronics manufacturers, as well as providing contract design services for hardware and software, and as a partner in customer product development, from specification studies to trial production. They support development and mass production. PALTEK will contribute to the development of their customers by providing optimal solutions for them based on their corporate philosophy of “coexistence with diverse entities.”
For more information about PALTEK, please visit https://www.paltek.co.jp.
Inquiries regarding this matter
Edgecortix Public Relations Officer：email@example.com / 03–6417–9661