Arm Cortex-M Processors — An Overview
ARM stands for Advanced RISC (Reduced Instruction Set Computer) Machine and was founded in 1990 in California. Best known for its range of RISC processor cores design, fabric IPs, software tools, etc.
There are primarily 3 types(based on the market segment) of processors which Arm offers:
Securcore is just an extension of Cortex-M.
Below are the recent and widely used Arm architectures.
Based on their relative performance, Cortex-M processors can be classified as :
Arm Cortex-M0
It is a small and simple processor that implements the ArmV6-M ISA. Supports Thumb (16-bit opcode) architecture.
Has 13 GPRs(General Purpose Registers) and 3 special registers -Stack Pointer, Link Register, and Program Counter. Supports 3 stages long pipeline(Fetch-Decode-Execute). Has Nested Vector Interrupt Controller(NVIC) for interrupt handling.Permits 32 general interrupts and one very high-priority non-maskable interrupt.
For debugging-external hardware has a breakpoint(to trigger a debug event at a particular instruction ) and a watchpoint (to trigger a debug event when a particular data location is touched by code ). A DAP(Debug Access Port) is provided with each Cortex-M processor as a debug interface.
To access internal memory-mapped peripherals, the processor allows an internal bus interconnect, and for external, the von-Neumann-styled memory interface that implements the AMBA 3-AHB lite protocol is used.
Supports two sleep modes-regular: saves dynamic power by getting most of the clocks and deep sleep mode: for deep power saving and static leakage power saving with the use of a Wake-up Interrupt Controller(WIC).
Arm Cortex-M0+
In many ways, it is similar to arm Cortex-M0 with some additional features and microarchitectural changes. Supports optional user/privileged mode for OS. Has an optional MPU(Memory Protection Unit) so that user tasks use only memory permitted to the task and does not interfere with OS memory or memory belonging to other tasks.
Only 2 stages long pipeline. Has an optional low latency single cycle I/O port compared to two or more cycles required for an AHB transfer .
One major Additional feature is MTB(Micro Trace Buffer)-for storing trace of execution path through program code which can be used for debugging purposes.
ARM Cortex-M1
Similar to Arm Cortex-M0+ but targeted at use on FPGA rather than in a full implementation flow.
ARM Cortex-M3/M4
Implements ArmV7-M ISA. It is a Thumb (16-bit) Instruction Set but supports a wide range of 32-bit instructions compared to V6-M.
Supports Harvard architecture -different memory interface for Code and Data. More permitted interrupts can be configured on distinct levels of priority.
