Analysis of Fault Tolerant Systems in QCA based VLSI Circuits :
So the previous blog was an introduction to Quantum-Dot Cell Automata based VLSI designs. We also saw the how the fault tolerant design of QCA based XOR-Gate and One-bit full adder. Let us analyze these designs further. The fault-tolerance and performance analysis of the proposed QCA-based designs of 2-input XOR gate and 1 bit full adder has been carried out. They computed the fault tolerance in terms of various faults like single cell omission, double cell omission, extra cell deposition, and cell displacement faults.
For QCA based XOR-Gate
Single Cell Omission faults :
We have computed the single cell omission faults for all of the Quantum dot cell automata cells in the proposed designs. The conventional design approach-based XOR gate of above figure has only 14 instances of fault free outputs out of total 29 instances of single cell omission. The fault-tolerance ability is 46.6%. The proposed fault-tolerant design of XOR gate of above figure has 56 instances of fault-free output out of total 67 instances, achieving a fault-tolerance ability of 84.6%. The fault-tolerance ability of the proposed QCA-based fault-tolerant 2- input XOR gate for single cell omission faults has been improved by 81.54% due to the addition of redundant QCA cells.
Double cell omission faults :
The double cell omission faults for all QCA cells in the proposed designs have been computed. The conventional approach based XOR gate model shows fault tolerance only once out of total 27 cases of double cell omission. The fault-tolerance ability is only 3.7%. The ‘XOR’ output in the proposed fault tolerant design of 2-input XOR gate has 56 instances of fault-free outputs out of total 94 instances, achieving a fault-tolerance ability of 59.57%. The fault-tolerance ability of the proposed fault-tolerant XOR gate for double cell omission faults has been improved significantly due to the addition of redundant QCA cells.
Extra cell deposition faults :
The influence of extra cell deposition faults on the functionality of 2-input XOR has been analyzed. It is assumed that extra cell is deposited in rectangular layout area, which is not utilized for deposition of QCA cells in the proposed designs. The ‘XOR’ output in conventional design approach-based XOR gate has 62 instances of fault-free outputs out of 64 instances of extra cell deposition. The fault-tolerance ability is 96.87%. The proposed fault-tolerant design of XOR gate demonstrates 100% fault tolerance ability against extra cell deposition faults.
For QCA-based one-bit full adder :
Single Cell Omission faults :
The ‘Sum’ output in the proposed conventional design approach-based 1-bit full adder in above figure has only nine instances of fault-free outputs out of 41 instances, achieving a fault-tolerance ability of 21.95%. The ‘Cout’ output shows fault tolerance 30 times of correct outputs out of total 41 cases, which gives a fault-tolerance ability of 73.1%. The ‘Sum’ output in the proposed fault tolerant model of one-bit full adder in above figure has 96 cases of accurate outputs out of total 111 instances, achieving a fault-tolerance ability of 86.48%. The ‘Cout’ output in the proposed fault-tolerant design has 107 instances of correct output out of total 111 instances, achieving a fault-tolerance ability of 96.39%.
Double cell omission faults :
The ‘Sum’ output in the proposed conventional design approach-based 1 bit full adder has no case of fault-free output out of total 33 instances, Thus, having no fault-tolerance ability for double cell omission faults. The ‘Cout’ outlet has 21 cases of accurate outputs out of 33 total cases, which gives a fault tolerance model with an ability of 63.63%. Similarly, the ‘Sum’ output in the said fault tolerant design of one-bit full adder has 103 cases of accurate outputs out of total 156 cases, by which we achieve a fault-tolerance ability of 66.02%. The ‘Cout’ output in the mentioned fault-tolerant design has 139 cases of accurate outputs out of total 156 cases, thus we achieve a fault-tolerance ability of 89.1%
Extra cell deposition faults :
The ‘Sum’ output in conventional approach design based one-bit full adder has a good 45 cases of accurate output out of total 53 cases, which leads to a fault tolerance ability of 84.9%. The ‘Cout’ output in proposed system has 50 cases of correct outputs out of 53 instances, achieving a fault-tolerance ability of 94.33%. Similarly, the ‘Sum’ output in the proposed fault-tolerant design of 1 bit full adder has 78 instances of correct output out of 80 instances, achieving a fault-tolerance ability of 97.5%. The ‘Cout’ output in the proposed fault-tolerant design has 100% fault-tolerance ability.
