FGPA based Fault Tolerant Techniques in VLSI Circuits
Triple Modular Redundancy(TMR) Design
In TMR design A voter is made up of simple logic gates and is capable of detecting errors when the inputs are inconsistent. It does not have to deal with a large number of errors per unit time. The TMR design assumes that we will not see identical errors on two processors at the same time. The voters cast the majority vote, so if the errors are identical, they will not be detected and, in fact, will be shown as truth
In the CFTP(Configurable Fault Tolerant Processor), it is designed to be fault tolerant by software. Its circuit must be capable of detecting errors on its own. To accomplish this, the concept of a voter is created. Below Figure depicts the appearance of a 1-bit voter. It’s a simple circuit made up of only AND and OR gates.
Because the voter will choose the majority of identical bits as the output bit. As a result, if two or more inputs are incorrect, the voter output will be incorrect as well. A system’s ability to detect and correct two or more errors in a voter is not required (e.g., the CFTP).
Assuming a single error, the output is always correct, but we can’t tell if there was one by looking at it. As a result, some additional gates are added to report the occurrence of an error. When one of the inputs is not identical, the error detection is 1.
Reference:
1.FPGA Based Multiple Fault Tolerant and Recoverable Technique Using Triple Modular Redundancy (FRTMR), 7th International Conference on Communication, Computing and Virtualization 2016.
