Implementing Micro Rollback in a Simple Synchronous System
As discussed in the previous stories, parallel error checks require the receiver to be able to roll back its state to undo state changes that are due to data which has turned out to be erroneous. Special circuits must be added to the module for preserving the state information and for executing micro rollback. There are two general techniques for rolling back the state of a typical synchronous system: the first one is used for the state of a collection of registers that are physically grouped together (e.g. register files), the second one applies to individual registers which are distributed across the chip (e.g. various status registers).
Micro Rollback of a Large Register File
The state of a large register file can be preserved for N cycles by simply replicating the storage N times and copying the current values to the ‘‘oldest’’ replica every cycle. This method can be very costly in terms of area. For example, the area of one copy of the register file in the Berkeley RISC II processor takes up 33% of the total chip area. There is an alternative technique that takes advantage of the fact that only one register out of the set can be modified every cycle. An example of this technique is shown in the figure below.
Every time a write is performed, the data and its full register address are stored in a FIFO buffer, which is called as the Delayed Write Buffer (DWB). Depending on the maximum latency (N) of errors signals, the write into the ‘‘real’’ register file is delayed for N cycles. During a read, the DWB is scanned in parallel with the register file in order to provide the most recent update of a register. At each cycle, all the data in the DWB is shifted one position to the left. A valid value in the left-most cell is written into the conventional register file. When a micro rollback of C cycles is required, we simply invalidate the last C entries in the DWB. By invalidating the last C writes, the state of the register file is brought back to the state it had C cycles ago.
Micro Rollback of Individual Registers
The technique for implementing micro rollback of a register file cannot be used for individual registers, such as the program counter and various pipeline latches, which are physically far apart on the chip. Instead, in order to support micro rollback of up to N cycles, for each individual register there are N ‘‘shadow registers’’ which store its state for the last N cycles (see the figure below).
A pointer keeps track of the location in the shadow register set used for each backup. During a rollback, the pointer is decremented by the number of cycles to roll back and the contents of the state register is restored with the correct ‘‘old’’ value. The use of a RAM for the shadow registers allows a micro rollback to be achieved in one cycle (compared with up to N cycles for a stack).
References
- Y. Tamir, M. Tremblay and D. A. Rennels, “The implementation and application of micro rollback in fault-tolerant VLSI systems,” [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers, 1988, pp. 234–239, doi: 10.1109/FTCS.1988.5325.
- Tamir, Y., & Tremblay, M. (1990). High-performance fault-tolerant VLSI systems using micro rollback. IEEE Transactions on Computers, 39(4), 548–554. doi:10.1109/12.54848
