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        <title><![CDATA[Stories by İlkbal Vildan Alkaya on Medium]]></title>
        <description><![CDATA[Stories by İlkbal Vildan Alkaya on Medium]]></description>
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            <title>Stories by İlkbal Vildan Alkaya on Medium</title>
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            <title><![CDATA[PROJECTS]]></title>
            <link>https://medium.com/@ilkbalv.alkaya/projects-1429ce681b0?source=rss-d670a7e8b24------2</link>
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            <category><![CDATA[projects]]></category>
            <dc:creator><![CDATA[İlkbal Vildan Alkaya]]></dc:creator>
            <pubDate>Sat, 09 Sep 2023 20:54:10 GMT</pubDate>
            <atom:updated>2023-09-10T16:29:20.221Z</atom:updated>
            <content:encoded><![CDATA[<h3><strong>INTERNSHIP PROJECTS</strong></h3><p><strong><em>2022–2023 Spring</em></strong></p><p><strong>Long-term Intern at TUBITAK BILGEM BTE / Embedded Systems and VLSI Design Lab (B840)</strong></p><p>I have worked here as a long-term digital design intern for almost 3.5 months working on mostly signal processing and communication protocols.</p><figure><img alt="" src="https://cdn-images-1.medium.com/max/1024/1*KCY4okK2C6yHvNsZCEkLPg.png" /><figcaption>Figure 1- Total Schematic of the whole project</figcaption></figure><p><strong>Custom FFT/IFFT IP: </strong>In the first part of my project, I took the FFT of the input signal , filtered the FFT, and then computed its inverse using Vivado’s <strong>Fast Fourier Transform</strong> (FFT) and <strong>BRAM</strong> intellectual properties (<strong>IPs</strong>). After that, I tested and packaged the project’s initial component as a custom IP. I have used <strong>Verilog HDL </strong>while completing this project.</p><figure><img alt="Figure 1- Project Schematic" src="https://cdn-images-1.medium.com/max/1024/1*fFE4QKQTGoC8YOyl-7kZQA.png" /><figcaption>Figure 2- Custom IP part of the project</figcaption></figure><p><strong>UART/FIFO/VGA: </strong>In the second phase of the project, a UART interface operating in the loopback mode was designed and tested on the PL pmod part of the Zedboard. Then I have designed FIFO for buffering and VGA part of the project. To sum up, I intended to use a monitor to display the sine wave output from the first project using VGA. All of the implementations of the projects were done on the ZedBoard.</p><figure><img alt="" src="https://cdn-images-1.medium.com/max/620/1*hpMeK9KbFjLExbdRZXiRiQ.png" /><figcaption>Figure 3- UART Design operating in the loop-back mode</figcaption></figure><figure><img alt="" src="https://cdn-images-1.medium.com/max/1024/1*f-Gbtnka6kfLwmyU2QI_mQ.png" /><figcaption>Figure 4- PL Pmod UART Interface</figcaption></figure><p><strong><em>2022–2023 Summer</em></strong></p><p><strong>Short-term Intern at Aspilsan Enerji A.Ş. / R&amp;D Department</strong></p><p>I have worked here as a short-term intern for 30-workdays. I have mostly worked on designing basic circuits of power electronics which are converter circuits (buck/buck-boost/flyback converter) and designed a Battery Management System.</p><h3>CAPSULE PROJECTS</h3><p><strong><em>2022–2023 Fall</em></strong></p><p><strong>Design and Implementation of an SCR Pulse Circuit, Controlled Full Wave Rectifier, Shunt Current, Measurement Circuit, DC/DC Boost Converter, DC Motor Drive: </strong>The design and implementation of these circuits are done according to the specifications. <em>(PSIM, LTspice, MATLAB Simulink)</em></p><p><strong>Real-time Audio Signal Processing on Zedboard FPGA: </strong>The hardware that the system is implemented on is the Zedboard development board with Zynq®-7000 All Programmable SoC. I have used PL and PS part together. I filtered the audio signal, added some noise, and then removed the noise basically using buttons on the board. <em>(Vivado, VHDL)</em></p><p><strong>Senior Design Project: </strong>Energy harvesting with triboelectric nano-generators. After the energy harvesting part, we tried to store it. First, we have rectified the signal and give it to the boost converter so that we can get a more stable voltage and current to charge a battery. We have controlled the converter circuit with STM32 F103C8.</p><p><strong>2021–22 Spring</strong></p><p><strong>Single Phase Transformer Design:</strong> Designing and optimization of a single phase 0.5 KVA 220 / 110 V, 50 Hz transformer with maximum efficiency and minimum cost (ANSYS Electronics Desktop) 4 pole PM Machine Design: Designing and optimization of a 4 pole 100W synchronous PM machine at 1500rpm, 50V peak, 1A peak with maximum efficiency and minimum cost <em>(ANSYS Electronics Desktop)</em></p><p><strong>Find &amp; Grasp an Object by Husky Robot using ROS:</strong> Finding and grasping the object on the conveyor belt with sensors mounted on the manipulator while moving the Husky <em>(Visual Studio Code, ROS, Ubuntu, VMware, Gazebo)</em></p><p><strong>Senior Design Project:</strong> Triboelectric based Energy Harvesting, PDMS &amp; Kapton materials are used to generate the TENG which converts mechanical energy into electrical energy.</p><p><strong>2021–22 Fall</strong></p><p><strong>Line Follower Robots:</strong> Construction of two line-follower robots and controlling it with PID via STM32F103C8. <em>(Keil, STM32CubeMX)</em></p><p><strong>Frequency to Voltage converter circuit:</strong> Design of a system giving an output voltage proportional to the frequency of a fan via photodiode current. When laser pointer passes the fan blades and activates the photodiode, rotation frequency and output voltage is displayed. <em>(LTspice, MATLAB)</em></p><p><strong>Pressure Sensor Design:</strong> Design and fabrication of a pressure sensor by using graphite and design of a circuit to read its capacitance value via Arduino. Characterization of the sensor, monitoring it with MATLAB GUI app. <em>(ANSYS, LTspice, MATLAB)</em></p><p><strong>2020–21 Spring</strong></p><p><strong>Vending Machine and 32-bit Microprocessor: </strong>A simple vending machine is designed and simulated in Vivado using VHDL. In addition, a RISC type microprocessor that operates with a basic set of operations is designed and simulated in Vivado. <em>(Vivado, VHDL)</em></p><p><strong>Roll Dice Circuit Design: </strong>Design of a circuit called roll dice which gives the output only between 1–6 using logic gate structure with CMOS configuration. <em>(LTspice, Logic.ly)</em></p><p><strong>2020–21 Fall</strong></p><p><strong>EEG Signal Processing Application: </strong>Design of an application via GUI which monitors the real-time analysis and recorded signals by request of a user. EEG data analyzation and design of a circuit that amplifies, filters, digitalizes the analog signal. <em>(LTspice, Proteus, MATLAB)</em></p><p><strong>2019–20 Summer</strong></p><p><strong>AC/DC Adapter Design:</strong> Design of an adapter according to the specifications. <em>(Proteus, LTspice)</em></p><p><strong>3-band Audio Equalizer Circuit Design: </strong>Design of an equalizer using <em>Proteus</em>.</p><p><strong>2019–20 Spring</strong></p><p><strong>Toy Car Motion Analysis</strong> <em>(Video Tracker)</em></p><p><strong>Projectile Motion and Collision</strong> <em>(Video Tracker)</em></p><h3>VOLUNTARY PROJECTS</h3><p><strong>Undergrad Research Projects</strong></p><p>I have worked on neural network using Python and MATLAB.</p><p><strong>TUBITAK 2247-C (STAR)</strong></p><p>TUBITAK scholarship for 6 months. I have worked on a project using ANSYS Lumerical FDTD.</p><img src="https://medium.com/_/stat?event=post.clientViewed&referrerSource=full_rss&postId=1429ce681b0" width="1" height="1" alt="">]]></content:encoded>
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