FPGA Prototyping, Edge-AI Processors, and HBM3: The Synopsys October Blog Roundup
By: Editorial Team
We’re looking back on some of our top blogs of the month of October. The rapid evolution of technology is bringing about endless possibilities and applications, powered of course by innovative chip designers.
This past month, our experienced thought leaders covered several forward-looking topics related to the semiconductor industry, from investing in high-bandwidth memory to the importance of embedded processor IP. Dive deeper to learn more about these trends and how Synopsys’ cutting-edge solutions are powering the era of Smart Everything.
1. Unified Power Format (UPF) and Beyond: How to Expand Low-Power Signoff
In this blog, two of our applications engineers, Nikhil Amin and Harsha Vardhan, discuss how the United Power Format (UPF) standard has played an integral role in the power landscape and created a wide range of opportunities for the electronics industry to develop power management techniques. As low-power design continues to rise in priority for chip manufacturers, designers will have to play the long game by investing in advanced power management techniques.
2. High Debug Productivity Is the FPGA Prototyping Game Changer: Part 2
Rob Parris, one of our verification engineers, explores the multitude of challenges designers face when performing RTL debug using an FPGA prototyping system. From high turnaround time to the sample depths of signals being insufficient, Synopsys’ HAPS-100 tackles these obstacles head-on with 4x performance and more, enabling developers to achieve high debug productivity levels to make design debug easier.
3. HBM3 Will Feed the Growing Need for Speed
With advances in technology comes data-intensive applications which need high-bandwidth memory (HBM) interfaces to move data between the system’s processor and its memory. According to two of our experts, Graham Allan and Vikas Gautam, avoiding memory bandwidth bottlenecks requires chip manufacturers to make key HBM design considerations now if they want to keep pace with increasing demand for faster speeds and lower power consumption.
4. Smarter Ways to Meet Your PPA Targets for Edge AI Processors
AI’s impact on technology is impossible to deny, but many don’t realize AI’s influence on smaller scale devices. Ubiquitous in our everyday lives, on-device edge AI can instantly and effectively process data and make predictions. Gordon Cooper, one of our technical experts, delves into how embedded vision processor IP can support chip designers in their quest to deliver high performance within very tight power and area budgets.
5. 7 Tips for Benchmarking Embedded Processor IP for AI SoCs
In this post, Gordon Cooper once again provided some key considerations for benchmarking neural networks and selecting embedded processor IPs for AI SoCs. In a compute-intensive world, it’s imperative for chip designers to be able to integrate the best AI-enabled processor and neural network accelerator into their systems. Synopsys solutions such as DesignWare ARC® EV Processors and DesignWare Memory IP aid in the process to provide predictable power, area, and performance.
To view full-length versions of these articles along with other solutions-based pieces, visit our From Silicon to Software Blog.
