An Efficient Hardware Implementation of Canny Edge Detection Algorithm

The canny edge detection is proven to be able to significantly outperform existing edge detection techniques due to its superior performance. Here the proposed method of author uses approximation methods to replace the complex operations; the pipelining is employed to reduce the latency.

In proposed design strategy the following are the keybcontributions:
i) Approximate methods for the computation of gradient
magnitude and orientation.
ii) Cumulative histogram based median filter architecture for
sliding window.

Finally, this algorithm is implemented on Xilinx Virtex-5 FPGA. When compared with the previous hardware architecture for canny edge detection, this architecture is requiring fewer hardware costs and takes 1ms to detect the edges of 512x512 image. The proposed design is mainly focused on Approximate methods for the computation of gradient magnitude and orientation and Cumulative histogram based median filter architecture for sliding window. The proposed canny edge detector uses the pipelining technique and handles the multiple blocks at the same time. It helps to achieve fastest working speed. The proposed algorithm is scalable and has high accuracy. It can be able to detect all psycho-visually important edges of the image.

Reference:

D. Sangeetha and P. Deepa, “An Efficient Hardware Implementation of Canny Edge Detection Algorithm,” 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Jan. 2016, doi: 10.1109/vlsid.2016.68.

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