FPGA Over ASIC For Canny Edge detection

The Canny edge detector is an edge detection operator that uses a multi-stage algorithm to detect a wide range of edges in images. It was developed by John F. Canny in 1986. Canny also produced a computational theory of edge detection explaining why the technique works.

The general criteria for edge detection include:

  1. Detection of edge with a low error rate, which means that the detection should accurately catch as many edges shown in the image as possible
  2. The edge point detected from the operator should accurately localize on the center of the edge.
  3. A given edge in the image should only be marked once, and where possible, image noise should not create false edges.

Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks.

ASIC and FPGAs have different value propositions, and they must be carefully evaluated before choosing anyone over the other. Information abounds that compares the two technologies. While FPGAs used to be selected for lower speed/complexity/volume designs in the past, today’s FPGAs easily push the 500 MHz performance barrier. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever-lower price points, FPGAs are a compelling proposition for almost any type of design.


Amara, Amara, et al. “FPGA vs. ASIC for Low Power Applications.” Microelectronics Journal, vol. 37, no. 8, Aug. 2006, pp. 669–677, www.sciencedirect.com/science/article/abs/pii/S0026269205003927, 10.1016/j.mejo.2005.11.003. Accessed 19 May 2021.



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