FPGA implementation of the Harris Corner feature detector
In computer vision, the Harris corner feature detector is one of the most essential early steps in many useful applications such as 3-D reconstruction. However, if it is implemented in software, the resulting code is probably not able to be executed in real time under low cost mobile processors.
In this blog we are going to discuss about one system in which the Harris corner feature detection is done using FPGA in Verilog.
FPGA used for this particular system is Xilinx xc7z020-clg484–1, which is an SoC consisting of FPGA slices and a due-core ARM Cortex-A9 processor. The camera registers are initialized through the SCCB interface. The camera will convert its Bayer pattern data to the 16-bit RGB565 format, and output in two clock cycles though the 8 bit data bus, together with line and frame synchronous signals. The image resolution is 640 480 and frame rate is 60 fps. The camera data capture-module will convert the separated data back to the16-bit RGB565 format. The Harris corner feature detector will output the corner feature result and the image for display. Due to the timing mismatch between the camera and VGA signal, a frame buffer must be inserted to separate the two clocked domains. and this is how corner is detected in Verilog using FPGA.
This system showed that using a modern FPGA it perform 60 frames per second Harris feature detection. Moreover, simulation experiment showed that the detection rate can goes up to 144 frames per second. So, this system can be used for Corner detection it’s speed of operation is high so as efficiency.
