Image Processing on FPGA using Xilinx AccelDSP

So, in this article we will be talking about some of the most fascinating technologies which have infinite possibilities in their domain. Namely VLSI, Machine Learning, Computer Vision, Artificial Intelligence and so on.

For every successful system we require some basic parameters such as efficiency, Clock Rate, Time required to complete task, Power requirement. So, in our article we are concentrating on these parameters using FPGAs for Image Processing.

So, above article presents design and implementations of image processing and its applications using FPGAs.

Xilinx AccelDSP is a software which is used for generating Hardware Description Language (HDL) from High Level Languages to improve implementation time. It is signal processing model synthesis tool offered by Xilinx which allows us to convert floating point into hardware module. Its most interesting feature is that a synthesizable RTL HDL model and Test Bench can be achieved.

Basically, it has 3 implementation options (Flows)

1) Default Synthesis flow

2) System Generator flow

3) HW Co-Sim flow

Generally, Default Synthesis flow is used. In this flow firstly floating points are analysed then according to design Fixed points are achieved. After achieving both are compared and RTL HDL model is designed.

Let’s discuss about its application in which colour conversion from RGB colour space to YCbCr colour space is implemented on FPGA using Xilinx AccelDSP.

YCbCr is a colour space method which is developed as a part of recommendation ITU-R BT-601 for worldwide digital components video stand is used in Television transmission. In YCbCr colour space, the luminance components are separated from colour components. Y is luminance component and Cb, Cr are colour components. Among all the colour model YCbCr seems to be better for skin detection.

These are the following steps which are carried out to convert RGB to YCbCr using Xilinx AccelDSP,

In general CSC design requires 380 CLB on the basic clock rate of 55.159 MHz but in above architecture it requires 323 CLB with the working frequency up to 83.271 MHz. Obviously, this architecture has lower complexity and improved efficiency in area. Thus, providing good choice in terms of low-cost hardware.

References:

“Using FPGA-SoC Interface for Low Cost IoT Based Image Processing” — Shivank Dhote, Pranav Charjan, Aditya Phansekar, Aniket Hegde1, Sangeeta Joshi, Jonathan Joshi