A few weeks ago at Architecture Day 2020, we shared details and plans for how Intel will continue to innovate across the six pillars of technology that will power our leadership product roadmap. Yesterday, we unveiled one of the best examples of that product leadership. With the announcement of 11th Gen Intel® Core™ processors with Intel® Iris® Xe graphics, codenamed “Tiger Lake,” we are able to show uncompromising, feature-rich products with leadership power efficiency and performance, supporting a myriad of platforms.
Through strong collaboration between Intel’s design and process technology teams, we are delivering innovations in both the metal stack and the transistor architecture. This high-performance and low-power process is critical to Tiger Lake, and the focus on process innovation is enabling new levels of performance.
With the advent of our 10nm SuperFin technology, we added a new high-performance 60 poly pitch transistor to the process that increases drive current with an improved gate process, enabling higher electron mobility while also lowering the source/drain resistance. The new transistor was used in the Willow Cove core, the high-speed coherent fabric, and throughout the memory subsystem. Additionally, the High VT devices were optimized for better leakage, performance and variation, and used in non-high frequency, leakage-sensitive critical IPs. By paying attention to the high-performance transistors, we lowered the voltage of operation everywhere. The V²-plus leakage benefit realized were key to delivering to additional performance and features to the customer. We used these new transistor capabilities to offer the operating frequency ranges of previous generations at lower voltages. We also used the power efficiency head room created to integrate additional IP to enhance the capabilities of all Tiger Lake platforms with features such as Thunderbolt™ 4, PCIeGen4 for direct-attached SSD and support for multiple double data rate (DDR) technologies from LP4, DDR4, to LP5 and larger caches.
In developing Tiger Lake, we designed a balanced process across both transistor and metal stack performance capabilities. Improvements to both are vital to ensure maximum scalable performance across the voltage frequency curve. High-speed transistors’ performance can be easily choked by a clunky, resistive metal stack. In many regards, the metal stack of Tiger Lake is the secret sauce.
We added two additional high-performance layers at the top and improved the resistance, yield ability, and availability of the mid-layers for better resistance and capacitance (RC). RC profile improved drastically in Tiger Lake, resulting in high performance and lower cost all without sacrificing transistor density. In fact, density improved, and so did the RC% profile. Our strategy to improve the performance of the metal stack has been proven with our results.
Super MIM Capacitor
We dramatically enhanced the performance of MIM-CAP by a staggering five times on Tiger Lake, providing better high current, Di/Dt mitigation, and power rail control for high-performance workloads. Intel’s MIM-Cap capabilities are second to none in the industry and manifest yet again how Intel has the ability to tune for performance in all areas with its IDM advantage.
The new Willow Cove CPU core added several new security features to protect against return-oriented and indirect jump target malicious code. We also redesigned the fundamental circuits to take advantage of the 10nm SuperFin process enhancements. In the end, we delivered performance improvement by dramatically lowering the voltage at which Willow Cove achieves its operating frequencies compared to Sunny Cove and extending the frequency range. Hence, you see massive gains in ST power unconstrained performance and TDP-limited performance.
The results for 10nm SuperFin are stunning. We opted to go this route rather than IPC investment as we could guarantee a performance improvement to nearly all workloads — and it paid off. All IPs were designed to benefit from lower Vmins that can be translated either into ISO Freq Power Reduction: 20% — 30% (for IPs which are not Vmin floor limited) or into ISO Power Freq Improvement: 15% — 25% across the various voltage domains. In Tiger Lake, the Willow Cove core turbo frequency improved by more than 20% and achieves 4.8 GHz, with more to come, on the XLT process — incredible!
The Willow Cove core increases the mid-level cache to 1.25MB — up from 512KB. We also added a 3MB non-inclusive last-level-cache (LLC) per core slice. A single core workload has access to 12MB of LLC in the 4-core die or up to 24MB in the 8-core die configuration (more detail on 8-core products at a later date).
The new Xe-LP architecture increases the execution unit (EU) count from 64 to 96 and delivers an architectural improvement in Cdyn of 30–40%. To ensure that the graphics performance of Tiger Lake could be fully unleashed, we redesigned the fabric and memory bandwidth capabilities to scale and support a >2x performance increase over Ice Lake in the same power envelope. (It’s those transistors and metal stack again giving design new capabilities. 😉) Tiger Lake ushers in a whole new level of PC gaming using integrated GPU in a very thin form factor. We’re talking 1080p, 30 FPS on popular, top-tier titles and in some cases much higher frame rates than that. Gaming is an easy way to evaluate graphics performance. But just as important, we enhanced content creation, such as auto reframing in video editing, upscaling photos, and color correction.
As I mentioned, Tiger Lake is not just about adding performance; it does that while also becoming more power efficient. Mileage will vary depending on the system, but we expect Tiger Lake to deliver an increase in battery life. What makes this so impressive is it is achieved with additional features integrated onto the die and fully upgraded IP across the board. The improved voltage at frequency in every domain is a key enabler. We achieved a 100mV system agent Vmin floor reduction — this is the largest system agent Vmin floor reduction in several generations of Intel client CPUs. We also added autonomous dynamic voltage frequency scaling to the high-speed fabric and memory subsystems along with several fully integrated voltage regulators (FIVR) for efficiency improvements. People will enjoy improved performance and a better experience on nearly every key battery life workload, such as 4K video playback and browsing.
Speeds and feeds are great, but the full experience is enhanced. People will enjoy better system responsiveness, instant resume time, and long battery life throughout their day with minimal disruption, in sleek, modern form factors.
Memory, IO, Display, Imaging, and Connectivity
We designed Tiger Lake to support emerging technologies as well. It supports LP4–4267 and DDR4–3200 for launch in the market this year, but will also support LP5–5400 as it emerges in client platforms in 2021. What about feature-rich IO? Well, we have that covered too! We have multiple type-C integrated ports supporting Thunderbolt 4, USB4, PCIe, and multiple display ports. In fact, Tiger Lake supports up to 8K display resolutions or multiple 4K displays in its lower mobile form factors. To improve power and responsiveness, Tiger Lake integrated a new x4 Gen4 PCI Express graphics port on all 9W and 28W SKUs, enabling SSDs to direct connect to the CPU vs. a slower PCIe connect off of the platform control hub (PCH). Tiger Lake further helped OEMs by adding x4 DP-In ports as well, letting them save precious board space with the newly integrate DP-In ports which enables more flexibility in form factor design.
We put great care into rearchitecting the display bandwidth and capabilities on Tiger Lake. A direct, isochronous connection from the display subsystem to memory was plumbed in to maintain a quality of service pipeline for high resolution displays. As a result, Tiger Lake supports up to four concurrent 4k60 HDR displays and can easily support emergent 8K resolution displays.
Tiger Lake continues the evolution of image processing capabilities. We added numerous image quality improvements as well as hardware-accelerated support for temporal de-noising and especially for new sensor technologies significantly improving support of HDR sensors and quality. The Tiger Lake imaging pipe supports higher throughput use cases with a complete high-quality, hardware-accelerated pipeline and is not dependent on algorithms running on the vector processors to provide the highest quality output. This marks the first IPU generation with an imaging pipeline fully implemented in hardware. Tiger Lake will launch with initial product support of 4K30 video and 27 megapixels still image with the architectural capability to scale in the future to as high as 4K90 and 42 megapixels.
Tiger Lake Chipsets: Delivering Lower Power and Enhanced Platform Capabilities
The chipset die within the Tiger Lake multi-chip package was key to achieving the extremely low modern connected standby (MCS) power in client products with integrated power delivery (FIVR). The PCH achieves deeper S0ix power states than available in previous client products, resulting in ~30% power reduction during the MCS workload. The key contributor to these results was Vnn removal, which internally removed voltage from all non-critical IPs, allowing only IPs such as CNVi, audio, and sensing to operate in these lower power states. The state for all the other IPs was saved internally, then restored such that platform software was unaware of the additional power actions taken.
Beyond this lower power innovation, the PCH continued to evolve technologies, shaping PC platform interaction and usage. WI-FI-6 (802.11ax) is integrated on a die, enabling which enables ~3x higher peak data rates1 and up to 4x capacity improvement2 over the prior standard. With the PC user experience increasingly becoming centered around speech and voice, Tiger Lake’s audio, voice and speech IP enables USB and BT audio offload, providing substantial power savings and enhanced battery life when using multimedia applications. The upgraded wake on voice capability enables the addition of more personal assistants, beyond Cortana and Alexa, aligning with Microsoft speech standard multi-voice assistant.
Security is an essential silicon offering. The Tiger lake PCH integrates the 4th generation converged security and manageability engine (CSME) that improves its crypto algorithms (SHA-384/512, RSA 3K/4K, ECC) to increase resistance to security attacks. It also implements special hardware circuitry that provides more resistance to power and electromagnetic side-channel monitoring. And it introduces control execution technology (CET) to the security processor to help protect against legitimate code misuse through control-flow hijacking attacks.
With the new PCH, we drove IO innovation extending past the traditional IO support standards such as PCIe, SATA, USB and others. Soundwire, and audio interface for low power and more flexibility in audio platform design were fully implemented for the first time. Touch host controller (THC) is Intel’s new generation low power, high response and high precision touch host controller. It supports simultaneous Pen + Touch for 2-in-1 designs that are verified as part of the Project Athena innovation program, and Tiger Lake’s two THC instances will also be used for dual and foldable screen laptops — such as the “Horseshoe Bend” concept device we showed earlier this year.
And Yes, AI
As deep learning workloads and programming paradigms advance, Tiger Lake offers a range of performance options from low to higher power. The low power demands of efficient speech recognition, dictation, and noise cancellation is offered with the new GNA 2.0 engine. The Willow Cove core supports the vector neural network instructions for general purpose AI programming which were introduced in Sunny Cove, but now implemented at even greater efficiency. The Xe graphics architecture has added int8 capabilities for a programming data operand density improvement of six times the performance over Gen 11 graphics architecture used to augment already dense FP32 and FP16 capabilities.
Tiger Lake was built to lead client mobile innovation into the next generation. The bar has been raised… again.
Notices & Disclaimers
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.
Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.
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