Technology
Building Intel’s Next-Gen Client Architecture — One Tile at a Time
By: Wilfred Gomes, Intel Fellow, Microprocessor Design and Technologies & Slade Morgan, Sr Principal Engineer
At the recent Hot Chips conference, my colleague Slade Morgan and I presented insights into how our upcoming Meteor Lake and Arrow Lake architectures are evolving. In this blog I’d like to detail how Intel’s key enabling technologies, which have been under development for decades, will come together in our high-volume PC client products to help flexibly deliver next-gen user experiences.
From our years of designing client architectures, we know that demands on client PCs are changing. The new era of system-based integration enables performance from Process, Packaging, Power Delivery, and Memory. We must drive overall co-optimization to be more agile, delivering solutions for a broader, richer set of experiences. We must be experience-driven, which means architects need to consider experiences first, working backward from the diverse user experiences and the corresponding design targets. In other words, performance needs to be purposefully curated for the experience. To do that, we need to be dynamic, allowing designers and product planners the ability to adapt quickly to changing markets. And we must be able to scale to a large number of design points and systems that support all these ecosystems. This means that client architectures going forward must be performance-driven — with a focus on both absolute performance and performance per watt — while simultaneously providing the ability to offer diverse intellectual properties (IPs) and support diverse functions.
One way to accomplish this level of agility is through disaggregation, i.e., utilizing multiple tiles to achieve higher flexibility while maintaining cost-effectiveness. These advantages must be weighed against a “performance tax” when comparing a disaggregated design against a monolithic processor, where keeping interconnects on-chip delivers the highest outright performance. This “performance tax” includes the latency, complexity, and power consumption required to move data from block to block.
We argue that it is now possible to deliver the best of both worlds: true monolithic performance with the benefits of a disaggregated architecture, targeted to high-volume manufacturing.
Intel’s disaggregation journey is nearly a decade long, along three technology paths: process technology, packaging advancements, and architecture. At every step on the way, we have learned, first from our client processor, Haswell, which packaged separate processor and supporting chip set tiles, on to Kaby Lake-G, which advanced to 2.5D Embedded Multi-die Interconnect Bridge (EMIB) packaging and added external foundry silicon for graphics. Lakefield employed our first-generation 3D Foveros packaging technology, which also introduced a hybrid architecture and multiple nodes.
Ponte Vecchio, has over 100 billion transistors and 47 tiles in a package, utilizing second generation Foveros and EMIB, and incorporating multiple process nodes from multiple fabs. Ponte Vecchio taught us how to create 3D architectures with very high yields and gave us the confidence to bring this technology to Intel’s client roadmap.
Innovation never stops at Intel. Foveros — our logic-on-logic 3D stacking technology – has an exciting roadmap, with product plans for Foveros Omni and Foveros Direct, which scale bump pitches, power, and IO per square millimeter. Foveros OMNI extends the Foveros technology to bring multiple base dies, multiple compute tiles and the ability to connect IO directly to the package using copper pillars for the highest performance parts. Foveros Direct will utilize direct copper-to-copper connections to dramatically reduce latency and increase density. This roadmap gave us the confidence to align Intel’s client roadmap to the roadmap for Foveros in future products.
We would like to delve a little bit deeper into the architecture and key blocks of Meteor Lake, as an example of how we are implementing this new flexible tiling and disaggregation. Our goal was to get disaggregation benefits not achievable with a monolithic design, while keeping disaggregation “taxes” to a minimum.
With the Meteor Lake architecture, we have a disaggregated core tile, a disaggregated graphics tile, an SoC tile for media, display, and other functions, and an extended IO tile. With the critical compute elements disaggregated we can spin the IPs and get them into the right process at the right time. Different products require different core counts, different mixes of Performance and Efficient cores, and different cache sizes.
With a disaggregated design, we have the flexibility to target each segment without disrupting the rest of the design. Over the life of the product family, new generations of the cores will become available, as well as new process nodes. With a disaggregated design we can pull in new compute cores as soon as they are ready, without disruption to stable parts of the design.
With the graphics tile, we can scale both the number of execution units and the cache sizes, bring in IP revisions and new process nodes. Our goal is to scale graphics performance from very low-power mobile to discrete-card-like graphics performance on the laptop.
The SOC tile is an ultra-low-power tile which supports media, imaging, display and the connection to memory, all of which can be targeted to the various market segments within mobile and desktop systems. It is a similar story with the IO extender tile, which can be adjusted to the target market segment.
To enable the assembly of multiple tiles Intel developed a high-yielding Foveros assembly scheme at 36 um pitch, which supports backside metallization. We can test each tile independently and put them together at high yields. There are 3D capacitors in the base die, fine pitch routing to enable low latency die-to-die connections and thick metal layers for power delivery.
The four tiles in Meteor Lake are attached to the base tile, which is the key to the overall solution. The base tile solves power delivery, die-to-die routing, and the ability to be modular with active silicon. To connect the tiles we chose a 36µm interconnect pitch. At this pitch, the power and latency taxes of disaggregation are very small, and we also get a very good attach yield. Whatever small penalty exists is easily overcome by the benefits that disaggregation brings. And as pitches scale further with new generations of Foveros, the performance tax (compared with a monolithic design) becomes smaller and smaller.
Looking forward, we will remain at the forefront with the successor to Meteor Lake, code-named Arrow Lake, where the construction remains the same and the tiles can be updated with the latest features and process nodes.
I am thrilled to note that multiple Meteor Lake parts — the first tiled, disaggregated architecture on the Intel 4 process — have booted and are working in our test labs. For Intel, this is a watershed moment. Thank you.
Visit the Intel process & packaging website to read more.
This blog is adapted from a presentation given by the authors at Hot Chips 2022. You can find the presentation and more at the Hot Chips website
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