Technology
Intel 4 is a milestone and a stepping stone
Author: Dr. Bernhard Sell, Vice President and Director of Specialized Technologies
The Intel 4 process details we unveiled at the annual VLSI Symposium in Honolulu this week is a milestone in the company’s path to five process nodes in four years announced nearly a year ago at Intel’s Accelerated event. With over 20 percent greater performance at the same power and with twice the density in high-performance library cells compared to the Intel 7 process, Intel 4 meets two critical goals at once: it meets the needs of new products now in development, including Meteor Lake for client, and it adds expertise and process modules that will be critical as we move further toward our objective of regaining process leadership in 2025.
But for Intel’s four-year path, how Intel 4 achieves these performance figures is just as important as the numbers themselves.
An obvious example is that Intel 4 offers significant shrinks in critical dimensions such as fin spacing, contact pitch, and lower-level metal pitches. This allows components to be fabricated closer together, potentially shrinking the size of library cells. It also has the potential to reduce path delays and to reduce power consumption.
But increased fin density had to be accompanied by significant improvements in the design of the FinFETs, involving refinements in materials and structure. These changes not only contribute to that 20 percent iso-power speed increase, but they are necessary steps on our way to the production of our RibbonFET gate-all-around transistors starting with Intel 20A, which is scheduled to be ready for manufacturing in the first half of 2024, followed by Intel 18A in the second half.
If metal line resistance were to rise out of control as we shrank features, delays and power could actually go up. So, the finer metal pitches had to be accompanied by a new metal recipe to reduce line resistance and electromigration. This reformulation delivers the interconnect delays and reliability we need but also builds expertise for Intel 3 and beyond.
And the ability to form patterns accurately is critical as we continue to shrink dimensions. Intel 7 already employed self-aligned quad patterning (SAQP) and Contact Over Active Gate (COAG) technology to improve density. For Intel 4 a new gridded layout scheme improves the fidelity of printed shapes. These and other improvements allowed the redesign of the high-performance libraries to shrink cells beyond what just the critical-dimension shrinks would have achieved.
But perhaps the most dramatic change in patterning is the extensive use of EUV for process simplification. Rather than employing EUV only on the most critical layers where we already have good solutions, we are using EUV in Intel 4 to sharply reduce the number of masks and process steps in some of the higher interconnect layers. This reduces process complexity. It also builds expertise and tool sets for future process nodes, where we will be using EUV even more extensively and where we will bring in the world’s first production high-numerical-aperture (High-NA) EUV systems.
That is Intel 4 in a snapshot. It is a significant new process node for Intel products. And it is a major step along our four-year, five-node path to regaining process leadership in 2025.
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