Another Big Jump in Performance and a New Name; This is Intel 7

Author: Chris Auth, Vice President and Director, Logic Technology Development

Intel Tech


Figure 1 — Intel 7 Metal Stack Cross section

Last year Intel introduced the Intel SuperFin 10nm process which enhanced the transistor and metal connection layers and introduced a higher-density MIM capacitor. Intel is continuing its advancements in process and packaging with a series of products and features. As part of these advancements, we are moving away from the previous naming and refreshing our lexicon to create a clear, consistent and meaningful framework to help the industry and our customers, including our foundry customers, make better-informed decisions. Our node naming is based on key technical parameters that matter to our customers, including process performance, power and area, and is based on a holistic assessment of improvement across these factors. For example, we’re expecting approximately 10–15% performance per watt increase with Intel 7 (over SuperFin) as we evolve the node — this is on top of the enhancements that the SuperFin process provided last year — and this total gain reflects more than a full technology node of performance gain since the 10nm technology was launched.

For area density, Intel 7 is comparable or more dense than similar external foundry nodes. Intel 7 will be shipping in products starting with Alder Lake for client products rolling out later this year, as well as Sapphire Rapids for data center, which will be in production in Q1 2022.

Let me explain what Intel has been doing to improve its logic technology, and why our latest process name better reflects how it compares with competitors.

Historically, in a typical technology node, the design rules were defined to reduce the vertical and horizontal dimensions by 0.7x each, which increases the area density by 2x. Along with that density improvement, the performance per watt improved as well.

The 0.7x scaling was the basis for the node naming multiplying each node name by 0.7x and was the basis for the 10nm name — 14 x 0.7 = 10. Here the naming didn’t recognize that the density of 10nm was aggressively scaled at 2.7x from 14nm providing an area density that is denser than similar external foundry nodes.

Since the introduction of the 10nm node, Intel’s performance per watt has increased a significant amount. In terms of both performance and density, Intel 7 is competitive with corresponding external foundry nodes. There are three main differences between what we are now calling Intel 7 and the SuperFin process.

Figure 2 — Intel 7 Transistor Cross section


First, we started with the transistor. For the Intel 7 transistor we have increased the strain introduced during the metal gate fill process, resulting in higher channel mobility, and the epitaxial source/drains have been tailored and optimized for reduced resistance and increased strain.

Intel pioneered the introduction of a strained silicon at the 90nm node with the epitaxy Source/Drain process. Since then, strained silicon has been a major contributor to logic performance throughout the industry. However, it has gradually become more challenging on the PMOS transistor to increase the strain by adding more germanium to the SiGe source/drain.

With the Intel 7 PMOS transistor we have improved the doping of the source/drain regions. For a high-performance PMOS transistor, both a high, abrupt Boron concentration to reduce resistance and a high grading of the Germanium without relaxing the strain in the source/drain are desired. If the grading is not perfect, it will relax leading to formation of defects in the lattice and less strain. The Intel 7 transistor achieves these goals.

On the NMOS side, historically there has been less strain in the system, which provides a bigger opportunity to add more strain. There are two ways that have been used to add strain in the NMOS devices, either through the doping in the source/drain or with a strain-inducing metal gate process. Intel introduced a strain-inducing metal gate process at the 22nm node and is extending this in the Intel 7 transistor with a more tensile gate material to increase the mobility of the channel.

On both NMOS and PMOS, careful attention has been given to the contact and spacer interfaces to minimize contact resistance and maximize the transistor drive current by optimization of the contact metal and spacer deposition processes. The combination of all of these methods result in markedly improved transistor characteristics compared to the SuperFin process.


In the Intel 7 interconnects, we reduced the capacitance at the critical M1 level of metal wiring by introducing a lower-k ILD (interlayer dielectric). When introducing a lower k ILD one of the biggest challenges is interaction with subsequent process steps which can increase the k value of the ILD. We carefully optimized our process to limit the amount of k value increase, reducing M1 capacitance by ~30%.

As part of the SuperFin process, we introduced a novel low resistance Via process at Via 2 and Via 3. The process involves using a thinner barrier layer to reduce via resistance while still providing the same barrier properties. For Intel 7 we have extended it all the way from Via 1 to Via 8, further reducing resistance in the interconnect stack.

Along with the lower via resistance, we reduced the interconnect capacitance from M2 through M9. Two techniques were employed to achieve this, first a high-density interconnect planarization process was introduced and, second, the via aspect ratio was increased. The result is that M2 through M9 capacitance was reduced with this combination of higher aspect ratio vias and novel planarization process.

Power Delivery

Servers depend heavily on power delivery, so we added a thick M14 layer for server products to improve power delivery and an additional ~20 percent increase in MIM density was introduced to the MIM capacitors. MIM capacitors which restore power when power droops occur are a critical feature for high performance processors. This is an additional ~20 percent on top of the 5x increase in MIM density that was introduced with the SuperFin process.

We have made a series of technology innovations which sharply improved the performance per watt for Intel processors, benefitting our customers and deserving of the name change to Intel 7. Explore more on how Intel is redefining compute through process and packaging innovations here.

Intel 7 Summary of Enhancements

Notices and Disclaimers:

  • Learn more about Intel node naming and process technologies at
  • All l product and service plans, roadmaps, and performance figures are subject to change without notice. Future node performance and other metrics, including power and density, are projections and are inherently uncertain and, in the case of other industry nodes, are derived from or estimated based on publicly available information.
  • Statements in this document that refer to future plans or expectations, including with respect to future technology and products and the expected benefits and availability of such technology and products, are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our press release dated July 26, 2021, and SEC filings at
  • Product performance varies by use, configuration and other factors. Learn more at
  • © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.



Intel Tech

Intel news, views & events about global tech innovation.