Hip-Hop it’s Flip-Flop! Part-II
Ever guessed why did a bit go to therapy? Because it had too many ‘identity crises’!
Picture this: Two bits walk into a logic gate, one says ‘0’, the other says ‘1’, and chaos ensues! It’s like a sitcom in silicon, a laugh riot in circuits! But fear not, for amidst the binary banter lies a nugget of wisdom about decision-making and digital dilemmas. So grab your sense of humor and join me on this hilarious journey through the byte-sized wonders of computing!
Welcome back my tech aficionados✨! Today we will be building the next part of our flip-flop. That is the D-Flip-flop. But basic question before we proceed will be “WHY?”. Previously we built a SR Flip-flop where we will ‘Set’ or ‘Reset’ according to our requirement. So, what if I provide a single input which could perform the function of SR Flip-flop without any distortion. This was my basic curiosity on starting this blog and I thought Why not take it and explore with our aficionados. So here I am!
Let’s start wi… Hey, I heard you! You are absolutely right. Why don’t we keep an inverter before a SR Flip-flop.
In this case, an impulse will cause the pulse to become “Set,” which will then become inverted as it rises, turning our “Reset” portion into “0.” And the other way around. Anyway, now that we have a sketch, let’s connect the components to see if our sketch is functional. You may be wondering, “Where do we get an inverter?” Well, as far as we know, this is the NOR Gate truth table.
As we can see, the result is ‘1’ if both inputs are ‘0,’ and ‘0’ if both inputs are ‘1’. Therefore, we can make it function as an inverter by tying both inputs together. It also lessens the need for additional chips.
In this case, our switch has one input connected to the first NOR gate, which I have labelled “1st.” Another input is connected from the same switch to the other NOR gate, which I have labelled “2nd.”
We can see from the above operation that while it complies with the rule, nothing is latching or being stored. Having an “Enable” input would be a better option for me to tell the latch when to latch and when to ignore it. The schematic for adding an enable pin to our SR latch is shown below.
Instead of directly ‘Setting’ and ‘Resetting’ directly through our NOR gate we would allow them to pass through an AND Gate on both ‘Set’ and ‘Reset’ part. But how is this gonna work? Come let’s figure it out😉!
If we have our enable pin ‘Low’ or ‘0’, regardless of whatever our inputs may be the output will be ‘0’. Why don’t we check the logic by building it🛠️
Now let’s power up the circuit. We can see the LED glowing so probably it might be in ‘Set’ state. Now as we can see in the below video, if we press the Reset button it does not work, WHY? Because we haven’t enabled. Now by pressing the enable pin we can switch the state and once after we switch the state and if we pull back our Enable pin, and if we try to change the state, it doesn’t work. This is where and how the role of Enable plays.
Fine. But let’s try this again with our inverter as we did previously to use only a single input. Anyway it will change only according to our Enable pin.
(ckt image after connecting inverter to enable ckt)
Here we can see there are 2 blue wire from down, which is our ‘Set’ and ‘Reset’ wires and they come from the AND gate and the inputs for those AND gates are, one input would be the Enable(top push button) and other inputs are represented by yellow wires(from the enable pin). The ‘D’ represented in the image the Data input I guess, will be the second switch, below the Enable switch. The green wires represent the connection to the AND gate. Let’s power up and check how it is gonna work?
We have positioned a red LED to indicate the state change. The video up above shows you that until we enable it, the state won’t change. As a result, our circuit can latch in addition to being able to “Set” and “Reset” without requiring multiple inputs. This D-Latch’s primary function or application may be in the computer’s memory unit. This works well for storing a single piece of data.
Hurray! We have built, tested and successfully got our desired result🥳🥳
In our future blog we will be exploring and building a 1 bit register and an 8 bit register. See you all soon, so until then it’s a bye👋🏻. Keep supporting by providing your valuable suggestions down in the comment section. And as I always say,
Your Support! Our Adventure❤️!!
Datasheet link: 74LS32 , 74LS02
Connect me through:
GitHub:-> https://github.com/PranavRajeswari
LinkedIn:-> https://www.linkedin.com/in/pranav-rajesh-9b694a241/
Gmail: pranav.mukundh@gmail.com
Circuit Diagram and Connection Credit: Abinaya Meenatchisundharam, BenEater.
