El Correo Libre 38

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LibreCores

13 min readMay 11, 2021

FOSSi Dial-Up is Back on Track

After some unfortunate delays, FOSSi Dial-Up is back. We launched our series of talks around “evolving communities” on April 27 and were joined by Wilson Snyder, the primary author of Verilator. Wilson talked the background of Verilator and how it grew out of an internal tool into the open source community 25 years ago. He also presented what he is currently working on and we had an interesting Q&A. You can watch the replay on YouTube.

The series will resume on May 25 with Philipp Wagner talking about the long path to a sustainable cocotb community. After some impressive first results, the project was dormant for some time, but since a few years it is under control by a group of maintainers that turned it into a vivid project. In this talk, Philipp will present a bit of history on cocotb, how maintaining popular software is challenging, and ways the cocotb project found useful to solve those issues. Of course we’ll also look at some of the newest features of cocotb and how they make verifying hardware even more productive.

Throughout June we will run a weekly event in the same time slot then where the successful participants of first Skywater Open Source PDK shuttle will present their results. We are really curious to learn about how it went for them and what the community can learn from them.

You can find more information about FOSSi Dial-Up and the upcoming talks on the FOSSi Foundation website.

-Stefan Wallentowitz, Director, FOSSi Foundation

Efabless, CHIPS Alliance Launch MPW-TWO Shuttle for Open Silicon Projects

Following the stellar success of MPW-ONE, the first entry in the Open MPW Shuttle programme to see free and open-source silicon projects produced as physical chips at zero cost to project creators and maintainers, Efabless and CHIPS Alliance have announced the deadlines for the second shuttle: MPW-TWO.

“MPW-TWO is the second Open MPW Shuttle providing fabrication for fully open-source projects using the SkyWater Open Source PDK announced by Google and SkyWater,” says CHIPS Alliance general manager Rob Mains. “The shuttle gives designers the freedom to innovate without having to worry about the risks associated with the cost of fabrication.

“This is a great opportunity for individuals, universities, and industry to create their own IP and have it manufactured. This opportunity comes after the success of having 40 submissions for the MPW-ONE shuttle; 60 percent of those designs were submitted by first-time ASIC designers.”

As with the first shuttle, MPW-TWO is open to any free and open-source silicon project providing it can be adapted to use the Caravel project’s common test harness and pad frame. Projects selected for inclusion in the shuttle will be produced at no cost on SkyWater’s 130nm process node.

The call for designs runs through to the 18th of June 2021, with interested parties asked to apply through the eFabless website; shipping, meanwhile, is expected to begin in early December.

Antmicro Announces RISC-V-Based “Fully Open Source” System-on-Module, ARVSOM

Antmicro has announced the finalisation of a system-on-module (SOM) design based around the free and open source RISC-V instruction set architecture — and is looking to make the device pin-compatible with the proprietary Raspberry Pi Compute Module 4 range to take advantage of its existing carrier board ecosystem.

“Since its conception, Antmicro has been enabling its customers to tap into the technological freedom that is inherent in open source,” the company explains in its pre-launch announcement. “We’ve been developing cutting-edge industrial and edge AI systems using vendor-neutral and customisable solutions as well as actively developing and contributing to the tooling ecosystem, improving processes and unlocking even more system design options — often in alignment with our efforts driving RISC-V International and CHIPS Alliance.

“Targeted at a range of different use cases and enabling unmatched flexibility, ARVSOM is the latest product and example of Antmicro’s expertise in creating practical and easily modifiable technologies using open source.”

The ARVSOM module itself, Antmicro promises, will be entirely free and open-source, though it’s built around a proprietary core: The StarFive 71x0 system-on-chip, a Linux-capable device featuring a dual-core SiFive U74 processor, SiFive’s in-house Neural Network Engine (NNE) and an Nvidia Deep Learning Accelerator (NVDLA), and peripherals including MIPI DSI and CSI interfaces, HDMI, gigabit Ethernet, USB 3.0, and PCI Express — the latter missing from early test chips but on the roadmap for production later this year.

More details on the ARVSOM, which is compatible with Antmicro’s own Scalenode platform as well as third-party carrier boards designed for the Raspberry Pi Compute Module 4 family, can be found in the official announcement. No launch date or pricing for physical hardware has yet been unveiled.

RISC-V International Launches Development Board Giveaway

RISC-V International has opened applications for zero-cost Linux-capable RISC-V development boards, offering between 1GB and 16GB of on-board memory, in an effort to encourage debugging, software porting, adoption, and promotion of the free and open source instruction set architecture.

“RISC-V is now being engineered into everything from soldering irons to supercomputers,” RISC-V International chief technology officer Mark Himelstein explains in the organisation’s announcement. “One step along the way is facilitating the availability of development boards for testing and development. We are inviting RISC-V members to sign up for a RISC-V developer board sponsored by RISC-V and our RISC-V contributing members. We have boards available and we want you to have one!

“What do we want you to do with the boards? Everything! Develop software, learn RISC-V, run tests, port software, look for ways we can improve, contribute — this is your opportunity to get your hands on RISC-V and engage in the RISC-V ecosystem!”

Supplied by RISC-V International member companies, the specifications of each board — offering largely similar CPU implementations but with 1GB, 2GB, 8GB, or 16GB of RAM — will be paired to the requirements of applicants, who are asked to provide information about their planned use-case in order to be paired with a board at no cost.

“We will be looking for your feedback,” Mark adds. “We’d also love to showcase your innovations, successes, and stories. Let us know so we can amplify on social media or perhaps a blog.”

Boards are available to RISC-V International members through the official application form; individuals and academics who are not yet members can apply for a free membership at the Community tier on the RISC-V International website.

“Massive” Renode 1.12 Release Brings More Platforms, Tests, and Demos

The latest version of the open-source Renode simulation framework, described by maintainer Antmicro as a “massive” release, brings with it a wealth of improvements in cluding support for additional platforms and devices, tests, and demos.

Chief among the new release’s features is broader support for additional free and open source silicon platforms, including the OpenTitan EarlGrey platform and a range of OpenTitan peripherals, platforms based on OpenHW Group’s CV32E40P along with a range of PULP peripherals, and the LiteX with RISC-V Ibex CPU platform.

The release also brings with it a selection of new tests and demonstrations, including tock demos for VexRiscv. “We’ve also improved capabilities of Python integration,” Antmicro explains, “allowing the use of the whole Python standard library from event hooks and peripheral mocks. This can be used to write even more complex workflows, e.g. by integrating Renode’s Python layer with external tools.

“The 1.12 release also brings new developments regarding co-simulation, such as multi-bus and AXI4 support (both as an initiator and a receiver) in co-simulation with Verilator, and the option to use verilated peripherals on Windows and macOS — improvements done in collaboration with with Microchip, while Renode’s robust testing and debugging capabilities have been extended with support for virtual addressing in GDB.”

More details on Renode 1.12 can be found in the official changelog, while the full source is available on GitHub under the permissive MIT Licence.

QEMU 6.0 Adds Multi-Process Support, Initial 32-bit on 64-bit RISC-V Support

The latest release of the QEMU emulator, version 6.0, has landed with a wide variety of new features and improvements — including “experimental” support for multi-process operation, the beginnings of support for 32-bit RISC-V CPUs on 64-bit software builds, and new documentation.

A major feature of the new release is early support for multi-process operation. “This work-in-progress, experimental feature is for multi-process QEMU,” Phoronix’ Michael Larabel writes of the new feature, which in QEMU 6.0 is available exclusively with a single emulator SCSI controller as a work-in-progress. “The goal with the multi-process QEMU is to run emulated devices in separate processes to increase overall security rather than having one large monolithic QEMU process.”

For those using QEMU to test and develop for the RISC-V instruction set architecture, the new release introduces the beginnings of support for emulating a 32-bit CPU while using a 64-bit software build on a 64-bit physical host CPU. Additional documentation for using RISC-V on QEMU has also been provided in the new release, and the quad SPI NOR flash on the Microchip PolarFire FPGA board is now supported.

More details, and a link to download the latest release under the reciprocal GNU General Public Licence 2, can be found in the official announcement.

Olof Kindgren Offers “A First Look at Edalize for ASIC Flows”

FOSSi Foundation director Olof Kindgren has published a first look at using Edalize for application-specific integrated circuit (ASIC) workflows — highlighting the latest in what he describes as the ongoing revolution in open-source silicon.

“We finally reached an important milestone last year where it’s now possible to create an ASIC using only open source code and tools,” Olof explains. “And within the limitations of the tools and technology this works just fine for one-off designs. Scaling this up has been a problem however. We see the same tasks being manually repeated and RTL files being copied over and over again instead of focusing on making more exciting end products.

“Aided by funding from the NLNet NGI0 PET fund, Qamcom is now extending Edalize with a new backend for ASIC implementations, starting with the OpenLANE flow. The work is being done primarily by Klas Nordmark and me. The overarching goal of the project is to allow users to quickly onboard their existing FuseSoC-enabled designs to the OpenLANE flow by just adding a bit of OpenLANE-specific information to the core description file, run FuseSoC and get a GDSII file, making it just as easy as it already is to create an FPGA bitstream or a simulation model.”

More details on the work, which Olof describes as “almost there” and which includes the development of a reference SERV-based system-on-chip dubbed subservient, can be found on Olof’s blog post.

Tom Verbeure’s Hack Offers Cross-Family RTL for Intel FPGA RAM Initialisation

Developer Tom Verbeure has detailed a novel approach to initialising memory in Intel FPGAs which allows for the RTL to be compatible with multiple FPGA families — a major improvement over Intel’s official approach.

“How can you quickly update bitstreams with new RAM content without going through resynthesis and place-and-route? I’ll describe 2 techniques,” Tom writes by way of introduction. “The official one, which requires hand-instantiation of an Intel FPGA RAM model and using a HEX or a MIF file; a hack that allows using Verilog inferred RAMs in Verilog that are initialized with $readmem(…).

“The first option uses an Intel altsyncram primitive and doesn’t work with FPGAs of vendors. The second option makes the RTL of your design compatible across different FPGA families.”

In addition to describing the two approaches in detail, Tom has also offered an example project: “A small but non-trivial example that contains a VexRiscv CPU,” he explains, “dual-ported RAM to store CPU instructions and data, and some peripheral registers to control LEDs and read an button. The example has been tested on my Arrow DECA FPGA board, but it’s easy to port it on other Intel FPGA boards.”

Tom’s full write-up is available on his blog, while the mini-CPU example has been published to GitHub under the permissive Unlicense.

This “Deceptively Simple LED Counter” Hides a Neat FPGA Reconfiguration Trick

Developer Sylvain Lefebvre has shown off the fruits of joint labour with Juanma Rico and Unai Martinez-Corral: what appears at first glance to be an LED counter on an iCEBreaker development board but, in reality, hides some very clever dynamic reconfiguration.

“Each step is a separate hardware design,” Sylvain explains of the LED counter demo. “The iCE40 FPGA dynamically re-configures itself. But there are eight designs, isn’t four supposed to be the max?! Something crazy is going on!

“This is achieved by dynamically manipulating the addresses stored at the beginning of SPI-flash, in particular the address in the second red rectangle. To do this, we install a bootloader in the first address. Each time the bootloader kicks in, it changes the second address to point to where the next design is in SPI-flash and resets to it. Each design goes back to the bootloader on button press. This is faster than swapping entire designs as ‘only’ the first 4KB are updated.”

The result: it’s possible to store as many designs as you can physically fit into SPI flash, and dynamically select from any or all of them in logic. “[With] a meta finite-state-machine across designs, with SPI-flash as shared memory,” Sylvain notes.

Sylvain’s full write-up on the project is available on GitHub, along with full source code.

Sylvain Lefebvre’s Silice Language Gets Improved Documentation, New Tutorials

While not otherwise engaged in packing dynamic configuration functionality into low-cost FPGAs, Sylvain Lefebvre has found time to improve the documentation in the Silice language for FPGA projects — including the additional of new tutorials.

“Silice simplifies prototyping algorithms on FPGAs,” Sylvain writes of the project, which was originally developed for personal use during the creation of soft-cores which are dedicated to running game engines like id Software’s Doom. “It provides a thin abstraction above Verilog (a typical hardware description language), simplifying design without loosing precise control over the hardware.

“It gives the (optional) ability to write parts of your design as sequences of operations, subroutines that can be called, and to use control flow statements such as while and break. At the same time, Silice lets you fully exploit the parallelism of FPGA architectures, describing operations and algorithms that run in parallel and are precisely in sync.”

In its latest release, the Silice documentation has been improved with a view to making it more accessible to newcomers. Combined with an introductory video and reference documentation, the tutorials showcase how Silice can be used to create projects on the IceStick, IceBreaker, and ULX3S development boards, “and many other boards with minimal changes.”

The latest documentation is available on the Silice GitHub repository, published under the AGPL-3.0 licence, with links to the tutorials at the bottom of the readme file.

Opal Kelly’s SYZYGY Project Releases Design Files for Template PCBs

Opal Kelly’s SYZYGY, which aims to create an open standard for high-performance peripheral connectivity based on low-cost connectors and cabling and with no licensing costs, has released design templates for compliant peripheral PCBs in Altium and KiCad formats.

“SYZYGY fills the gap between low speed, low pin-count Digilent PMOD devices and high-performance, high pin-count VITA 57.1 FMC peripherals,” Opal Kelly explains of the project’s aim. “Upon release, we intend to release the SYZYGY schematics, PCB layout artwork, and firmware sources as a reference design for other vendors to develop SYZYGY compatible carriers and peripherals.”

True to its word, Opal Kelly has now released PCB templates. “[The] template contains: SYZYGY Standard and Transceiver Connectors; MCU for SYZYGY DNA Support; Programming Connector (Tag-Connect); Standard Mechanical Configuration (Board length can be adjusted as necessary).

“The template boards support either the TC2030 or TC2030-NL. The exact cable model will depend on the programmer you are using as this changes the pinout and connector on the other end of the cable.”

The templates, which include parts libraries, are available now on the SYZYGY GitHub repository under an unspecified licence.