Gareth Halfacree
Mar 13, 2018 · 11 min read

¡Hola, amigos! Welcome to the first edition of El Correo Libre, the LibreCores newsletter.

Have you ever experienced this? You’ve arrived in a foreign country where you don’t speak the language. You feel a bit left alone, when soon enough a friendly stranger approaches you and shows you all the interesting places in town.

This newsletter, of which you’re reading the first ever edition, wants to be your guide and show you around in the world of free and open source digital hardware design. Which open source projects have released exciting new “IP”? What recent announcements paint an interesting vision? What events in industry will shape the ecosystem for the time to come? We invite you to join the tour. Be inspired by what happens in the world around you.

We from the FOSSi Foundation named this newsletter “El Correo Libre.” None of us are Spanish-speaking so, as in the story above, we’re stepping with this newsletter into areas we’ve not been before. To make it a success, we need your guidance. Let us know what content is interesting to you, and what you’d like to see improved. We’re looking forward to your mails at and to your comments on the blog.

If you like what you see you can get this monthly newsletter delivered directly to your inbox. Subscribe now!

— Philipp Wagner, FOSSi Foundation Director

This Month in Free and Open Source Silicon

The FOSSi Foundation is once again taking part in the Google Summer of Code (GSoC), serving as an umbrella organisation for a range of projects in the field of open silicon design, open-source electronic design automation (EDA) tools, and the related ecosystem.

Designed to pair students with mentors in the industry, and offering a stipend to fund their work, GSoC is a great partnership for the FOSSi Foundation. The official website includes a list of suggested projects from which both students and mentors are encouraged to take their pick, while suggestions for topics not covered therein are also welcomed.

“As a student you are free to base your project on one of these ideas, but remember that it is your idea we are looking for, and you should come up with an idea that you want to work on. As there are more student proposals than we have seats, a well-written project idea is important for us to judge whether we should choose you over someone else,” explains the FOSSi Foundation’s Stefan Wallentowitz. “It is also a good idea to get involved with the community early on to get a better feeling for what kind of project you want to do, and what already exists.”

Interested parties can find more information on the topic at Stefan’s blogpost, while other open-source silicon projects participating in the programme include the HDMI2USB project, Apertus and its Axiom open digital cinema camera, and

Anyone wishing to apply for a position on FOSSi’s GSoC mentorship, meanwhile, can request more details on the process from Student applications must be submitted ahead of the 27th of March deadline detailed on the official timeline.

Luke Valenty is set to launch a crowdfunding campaign for the TinyFPGA BX, the latest entry in his popular TinyFPGA family of low-cost open field-programmable gate array (FPGA) development boards.

Based around the Lattice iCE40LP8K FPGA, the TinyFPGA BX includes 7,680 four-input lookup tables (LUTs), 128Kb block RAM, two phase-locked loops (PLLs), 8Mb of flash with 5Mb available, and 41 accessible input-output (IO) pins with 24 broken out on its tiny breadboard-friendly circuit board.

“The full potential of programmable logic devices allows for even more ambitious projects than custom microcontroller peripherals. Recreate entire 8-bit computers from history, or design your own,” says Luke of the project. “If you don’t know what the big deal is with custom digital logic, then here’s a great way to learn.

“Place a TinyFPGA BX down on a breadboard and get to task interfacing it with LEDs, switches, rotary encoders, and any other peripheral, sensor, or interface you might like to try. The low cost of the BX and open-source ecosystem make this an excellent way to get started on a new adventure with digital logic.”

More information on the TinyFPGA family is available on the official website, while orders for the TinyFPGA BX at a price of $38 are due to go live on crowdfunding site Crowd Supply in the near future.

Those developing on the BeagleBoard platform, meanwhile, have their own alternative to the TinyFPGA range in the form of the ICE40-based BeagleWire cape add-on board.

Using the Lattice iCE40HX4K, a smaller chip than the TinyFPGA BX’s iCE40LP8K, the BeagleWire add-on features 3,520 LUTs, 80Kb block RAM, two PLLs, 32MB of SDRAM and 4MB of flash, and IO pins broken out into four peripheral module (Pmod) and four Grove connectors plus four LEDs, two push-buttons, and two DIP-switches on board.

“BeagleWire caters to open source and open hardware enthusiasts. All of its schematics, software, and examples are totally open,” its creators explain. “The BeagleWire can be a great learning tool in an educational environment that teaches FPGAs, Verilog, and Linux kernel driver concepts. It allows users to break away from large, proprietary FPGA toolchains by allowing the use of the open source Icestorm toolchain. BeagleWire integrates closely with the BeagleBone Black and has the backing of the community. Thanks to that, a new user can receive help from more experienced members of”

The BeagleWire is available to order now from Crowd Supply, priced at $85 a unit or $160 in a bundle with a BeagleBone Black and pre-flashed micro-SD card. Shipping is scheduled to begin in late May 2018.

Folknology Labs and myStorm have also launched the fourth generation myStorm ICE40 development board, known as the BlackIce II, a standalone development board with Arduino shield compatibility.

“As makers, we fell in love with IceStorm open-source Verilog toolchain back in 2015 and wanted to create a best of class independent open source hardware development board to fully use the IceStorm FPGA toolkit,” the project’s creators explain. “BlackIce is a leader in its class for open-source FPGA hardware, it’s IO capabilities exceed other Ice40 dev boards. It has been refined through 3 generations and has been proven in applications and deployment spanning over 2 years. It’s got some real pedigree!”

The BlackIce II design, based on the Lattice iCE40HX4K linked to 4Mb of external static RAM, includes an STM32L433 ARM Cortex M4 microcontroller to allow it to operate as a standalone development board, and includes six double and two single Pmod connectors plus headers for Arduino shields and the Raspberry Pi single-board computer’s general-purpose input-output (GPIO) header.

More information is available from the project’s Tindie store, where the boards can be purchased for $55. Details on the design changes can also be found on the official website.

Microchip has announced that it is to acquire rival Microsemi in a deal valued at $8.35 billion and which will give it control over Microsemi’s Mi-V soft-CPU and RISC-V ecosystem.

Founded in 1959 by engineers Arthur Feldon and Steve Manning as MicroSemiconductor, Microsemi has been a staple of the electronics world for decades. Early success in missile components gave way to a wealth of products from storage control and audio processing, but its younger rival Microchip Technology — itself founded in 1987 as a spin-off of General Instruments — has taken the lead and is now looking to save its rival from declining sales.

“We are delighted to welcome Microsemi to become part of the Microchip team and look forward to closing the transaction and working together to realise the benefits of a combined team pursuing a unified strategy,” says Steve Sanghi, chair and chief executive of Microchip, of the acquisition. “Even as we execute a very successful Microchip 2.0 strategy that is enabling organic revenue growth in the mid to high single digits, Microchip continues to view accretive acquisitions as a key strategy to deliver incremental growth and stockholder value. The Microsemi acquisition is the latest chapter of this strategy and will add further operational and customer scale to Microchip.”

The move will give Microchip full control over the Mi-V ecosystem, set up to boost adoption of the company’s various ‘soft-CPU’ intellectual properties (IP) and the open RISC-V architecture.

EE News Europe has published an interview with the RISC-V Foundation’s executive director, Rick O’Connor, in which the benefits of the instruction set architecture open, modular design are highlighted.

“It’s a clean-slate ISA that benefits from 30 years or more of research. We’ve kept what’s good and got rid of what was less successful,” Rick explains of the RISC-V ethos. “It’s also very tight, clean, small and modular. That means you can take the things you want and leave out what you don’t need. And because it’s open it is also extensible.

“There’s been a shift in how people architect processors. This is because Moore’s Law is not producing its traditional performance and power benefits. We’ve seen it for a while giving rise to the use of accelerator hardware and multi-node clusters for performance. Really [RISC-V is] a different model. It’s the modularity and that there are so many more degrees of freedom. You don’t have to carry the whole specification.”

The full interview, which includes reference to two major technology companies due to begin shipping RISC-V designs in volume in the near future, is available on the EE News Europe website.

Wenting Zhang has published a project which converts an analogue VGA input into ASCII art in real-time, using a Xilinx ML505 FPGA development board and some very clever code.

Brought to our attention by Hackaday, Wenting’s project takes up around 500 lookup tables on the FPGA to analyse an incoming VGA video signal and convert it into ASCII art — the artform dating back even earlier than physical teletype terminals to the days of bored typewriter operators looking to spruce up an otherwise dry document by creating illustrations from combinations of different letters and symbols available from a sorely limited character set.

A demonstration video shows that the device works best, unsurprisingly, on a two-colour video input with strong contrast between the background and the characters, but copes surprisingly well even when presented with full-colour live-action video to convert.

More information is available from the project’s GitHub repository, where Wenting has made the source available under the GNU General Public Licence v3.0.

The lowRISC project has announced a milestone release, 0.5, which is the first to include fully open Ethernet IP alongside the ability to boot from a network server.

Based on a RISC-V implementation from the University of California at Berkeley (UC Berkeley) lowRISC 0.5 is the first to include 100Mb/s Ethernet capabilities from an open IP, which is integrated deeply enough into the design to allow for booting from a remote file server as well as local storage.

Other enhancements which made it into the lowRISC 0.5 release include a preview of interrupt-driven device drivers in Linux, an optimised Secure Digital (SD) interface, support for the Network File System (NFS), and multiuser system support.

“Our main development focus currently is migrating to a newer version of the upstream Rocket chip design and reintegrating our changes on top of that,” the team says of its development roadmap, “but we felt that the integration of Ethernet support merits a release before that change.”

More information is available from the official website.

The RISC-V Foundation has issued a Call For Papers (CFP) ahead of the RISC-V Workshop in Barcelona this May.

“We’re seeking proposals for talks and poster presentations conveying recent activity in the RISC-V community at the upcoming RISC-V Workshop co-hosted by Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC),” the Foundation writes of its CFP. “Talks can be of two lengths (25 minutes and 12 minutes), and talk presenters are expected to also participate in the evening reception to allow extended discussion. All poster presenters will give a three minute poster preview.”

The RISC-V Workshop is to take place in Barcelona, Spain, on the 7th to the 10th of May 2018, with the deadline for submissions on the 25th of March. More information is available on the official website.

Dan O’Shea has published VGA1306, which adds VGA display output capabilities to devices designed around an SSD1306-based OLED display panel using a low-cost FPGA.

First showcased by Dan back in January on the Arduboy forum, the VGA1306 uses a Lattice iCE40HX1K FPGA to take video data from the Arduino-based Arduboy educational games console and generate a compliant VGA signal for direct connection to a monitor, projector, or other external display device.

A stock Arduboy design interfaces with a small 128x64 pixel organic LED (OLED) display panel via the Solomon Systech SSD1306 controller; Dan’s design replaces this controller and creates the VGA signal in its place, making it compatible with any device which would otherwise use the SSD1306, while a variant can be used to produce a VGA signal from original Nintendo Game Boy hardware.

“My hope is that this little board can also be a gateway for others to dip their toe into FPGAs,” Dan explains, “tweak the code, play around, etc.”

Dan has begun to publish the project on his GitHub repository, under the GNU General Public Licence 3.0.

The Parallel Ultra Low Power (PULP) Platform project has announced two major releases: Ariane, a Linux-compatible 64-bit application-class core design, and OpenPULP, its first multicore microcontroller design.

A joint project between ETH Zurich and the University of Bologna, the PULP Platform enjoyed considerable success with its earlier designs. OpenPULP and Ariane, though, go considerable beyond what the project has released in the past.

OpenPULP, the team explains, is an eight-core cluster microcontroller design with a new low-latency memory interconnect, an advanced direct memory access (DMA) engine, an event unit for hardware optimisation of parallel processing, a shared instruction cache for improved energy efficiency, and support for hardware-memory hardware accelerators.

Ariane, meanwhile, is the project’s first Linux-compatible 64-bit RISC-V application-class core design, designed for more computationally intensive workloads and boasting incoming support for all atomic extensions — something the team describes as a mandatory requirement for reaching the performance levels they desire.

Both OpenPULP and Ariane are available now on the project’s GitHub repository, under the SolderPad Licence v0.51.

Finally, Robert Baruch has begun a video series on his Learn Me A RISC-V 1 (LMARV-1) processor, designed to be as simple an implementation as possible and built with education firmly in mind.

Built entirely from medium- and large-scale integrated (MSI and LSI) circuits, each of which is labelled for its purpose, the LMARV-1 RISC-V processor is built to demonstrate the ease with which RISC-V can be implemented and also how it — and, by extension, processors in general — operates. LEDs along the top offer real-time feedback as the processor operates.

In his new video series, Robert walks through the LMARV-1’s various features in an accessible manner, beginning with the operation of its 32-bit registers. This is set to be followed in the future with additional videos which will be uploaded to Robert’s YouTube channel in due course.

Those interested in the LMARV-1 itself, meanwhile, can find more information on the project’s GitHub repository.

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News and features from the world of free and open source IP cores

Gareth Halfacree

Written by

Freelance journo. News editor, Author, Raspberry Pi & BBC Micro:bit User Guides. Custom PC columnist. Bylines in PC Pro, The MagPi, HackSpace etc.


News and features from the world of free and open source IP cores

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