El Correo Libre Issue 10
RISC-V Foundation Names Summit SoftCPU Contest Winners
The RISC-V Foundation has named the four winners of the SoftCPU Contest, held as part of the RISC-V Summit, with the Free and Open Source Silicon Foundation’s Olof Kindgren receiving the Creativity Prize for a RISC-V implementation dubbed SERV.
“The RISC-V ISA is ushering in a new era of innovation, empowering companies and designers around the world to develop a wide variety of implementations that solve today’s most complex design challenges,” claims Rick O’Connor, executive director of the non-profit RISC-V Foundation. “The RISC-V SoftCPU Contest showcased how embedded designers can easily experiment with RISC-V implementations on FPGAs, designing novel approaches even within a limited time frame.”
The other winners have been named as: Charles Papon for VexRiscv, Antti Lukats for Engine-V, and Changyi Gu with PulseRain Reindeer in first, second, and third places respectively. Entries were scored based on metrics including size and performance, with Lukats’ Engine-V using a mere 306 LUT4s.
Western Digital Announces Open SweRV Core, Supporting Technologies
Storage giant Western Digital has unveiled its first in-house processor design, SweRV Core, after pledging to ship more than a billion RISC-V based open cores each year — and it’s releasing it under an open-source licence.
As well as the SweRV Core 32-bit RISC-V implementation itself, which the company claims scales up to 1.8GHz with performance of 4.9 CoreMarks per megahertz, the company has also released two supporting technologies under open-source licences: the SweRV Instruction Set Simulator (ISS) and test bench, and the OmniXtend cache-coherent memory fabric.
“As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today’s wide-ranging data-centric applications,” claims Western Digital’s chief technology officer Martin Fink. “Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power.
“These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries.”
OmniXtend and the SweRV ISS are available to download now from the company’s GitHub repository, with the SweRV Core itself due for release in early 2019.
OpenISA Launches VEGAboard RISC-V Dev Platform with Hardware Giveaway
OpenISA has launched a new RISC-V development platform, the VEGAboard, and is encouraging adoption by offering limited quantities of the hardware free-of-charge to developers looking to investigate the RISC-V instruction set architecture.
Developed alongside the Parallel Ultra Low Power (PULP) Platform and industry members including Express Logic, Foundries.io, Ashling, IAR Systems, and Segger, the VEGAboard is built around an NXP Semiconductors RV32M1 chip which combines PULP RI5CY and Zero-RI5CY free and open source cores with proprietary Arm Cortex-M0 and M4 CPUs.
Designed with embedded development in mind, the VEGAboard design also includes an on-board radio supporting operation in Bluetooth Low Energy (BLE), frequency-shift keying (FSK), and IEEE 802.15.4 modes in the 2.36–2.48GHz range, 4MB of serial flash memory, and user-accessible hardware including a visible light sensor, digital sensor module with accelerometer and magnetometer, RGB LED, push-button switches, an OpenSDA serial and debug adapter, and general-purpose input/output on Arduino-compatible pin headers.
The board is being launched via a free giveaway on the official website, though is at the moment restricted to developers located in the United States of America. More information, including the software development kit, can be found on the project’s GitHub repository.
Microsemi, SiFive Announce PolarFire SoC Platform, Renode 1.6 Adds Support
Microchip subsidiary Microsemi, in partnership with RISC-V pioneer SiFive, has announced a new system-on-chip (SoC) platform dubbed the PolarFire SoC which combines the company’s field-programmable gate array (FPGA) hardware with an asymmetric coherent CPU cluster featuring four RV64GC RISC-V cores and one RV64IMAC monitor core.
“The PolarFire SoC architecture is a compelling combination of low power, security, and reliability in a configurable device that brings real-time to Linux,” claims Bruce Weyer, vice president of the programmable solutions business unit at Microchip, of the company’s creation. “Coupled with our robust Mi-V RISC-V ecosystem and Microchip’s extensive portfolio of system solutions, the PolarFire SoC architecture gives customers an excellent platform to meet computing’s next great challenges.”
“As a fully customisable, programmable RISC-V platform, the PolarFire SoC architecture gives designers the freedom to create innovative Linux-based SoCs in novel and interesting ways tailored for their distinct, domain-specific requirements,” adds SiFive chief executive Naveed Sherwami. “By leveraging SiFive’s market-leading U54-MC CPU core complex, PolarFire SoC will enable designers to overcome the universal challenge of building real-time systems with predictable behaviours.”
Simulation of the new platform is available in the latest Antmicro Renode 1.6 release, while a hardware development kit based on the SiFive HiFive Unleashed platform is available from Microsemi.
OpenPiton Announces RISC-V-Blended JuxtaPiton, OpenPiton+Ariane
The OpenPiton project, which has previously concentrated on the development of free and open source silicon based on the OpenSPARC instruction set architecture, has announced a pair of efforts which bring in support for the RISC-V ISA for the first time: JuxtaPiton and OpenPiton+Ariane.
“JuxtaPiton is (to our knowledge) the world’s first open-source, general-purpose, heterogeneous-ISA processor,” explains Jonathan Balkind of the project. “It is an enhancement to OpenPiton, built by integrating the PicoRV32 RISC-V core, written by Clifford Wolf, into the OpenPiton framework. JuxtaPiton inherits all of the capabilities of OpenPiton with the added ability to instantiate chosen tiles with RISC-V cores, rather than the usual OpenSPARC T1 core which uses the SPARC v9 ISA. The PicoRV32 core is connected to OpenPiton’s L1.5 cache, making it cache coherent with other cores in the system, thanks to our P-Mesh cache coherence protocol.”
Where JuxtaPiton combines OpenSPARC and RISC-V, however, OpenPiton+Ariane concentrates wholly on the latter ISA. “The Princeton Parallel Group led by David Wentzlaff, and the Digital Circuits and Systems Group of ETH Zürich led by Luca Benini have joined forces to bring you the OpenPiton open-source research processor platform with first-class support for 64-bit Ariane RISC-V cores,” Balkind continues. “Together, OpenPiton+Ariane provides the ideal permissive open-source RISC-V system that scales from single-core to manycore.”
More information is available from Balkind’s JuxtaPiton and OpenPiton+Ariane announcements.
Linux Foundation, RISC-V Foundation Join Forces for “a New Era of Open Architecture”
The Linux Foundation and the RISC-V Foundation have announced a pooling of efforts, working together to produce training programmes, infrastructure tools, community outreach initiatives, and even marketing and legal services to the RISC-V community.
“With the rapid international adoption of the RISC-V ISA, we need increased scale and resources to support the explosive growth of the RISC-V ecosystem. The Linux Foundation is an ideal partner given the open source nature of both organizations,” claims Rick O’Connor, executive director of the non-profit RISC-V Foundation, of the partnership. “This joint collaboration with the Linux Foundation will enable the RISC-V Foundation to offer more robust support and educational tools for the active RISC-V community, and enable operating systems, hardware implementations and development tools to scale faster.”
“RISC-V has great traction in a number of markets with applications for AI, machine learning, IoT, augmented reality, cloud, data centres, semiconductors, networking and more. RISC-V is a technology that has the potential to greatly advance open hardware architecture,” adds Jim Zemlin, executive director at the Linux Foundation. “We look forward to collaborating with the RISC-V Foundation to advance RISC-V ISA adoption and build a strong ecosystem globally.”
The first output of the joint initiative is a pair of introductory guides to using the Zephyr open-source real-time operating system (RTOS) on RISC-V platforms, unveiled during the RISC-V Summit last week but not publicly available at the time of writing.
Bootlin Publishes 64-bit RISC-V Cross-Compilation Toolchain
Embedded development specialist Bootlin has updated its cross-compilation toolchains with new RISC-V 64-bit support, giving developers an easy route to supporting the instruction set architecture.
“A RISC-V 64 bit toolchain is now provided,” explains Bootlin chief technology officer Thomas Petazzoni in the update announcement, “following the addition of support for this architecture to the Buildroot project.”
Other changes in the published toochains including a move from gcc 6.4.0 to 7.3.0, gdb 7.11.1 to 7.12.1, Linux kernel headers 4.1.52 from 4.1.49, glibc 2.27 from 2.26, musl 1.1.19 from 1.1.18, and uclibc 1.0.30 from 1.0.28 for the stable toolchains. Those looking for newer versions, including gcc 8.2.0, are directed to the toolchains’ bleeding-edge releases.
“We are still using a 7.x gdb version because the 8.x versions need C++11 support, which requires a recent enough host compiler, which in turn requires using a more modern distribution,” Petazzoni explains. “Thus, those toolchains would be unusable with older distributions as they would require a recent glibc version on the host. Currently, our stable toolchains are still built within an old Debian Squeeze system, for maximum compatibility with old distributions.”
All the toolchains, including the new 64-bit RISC-V toolchain, can be found on the company’s dedicated toolchains site.
GreenWaves Demonstrates GAP8-Powered Facial Detection System
GreenWaves Technologies has published a demonstration of a facial detection system running on its 32-bit RISC-V-based GAP8 ultra-low-power microprocessor, via the GAPuino development board.
“In this demonstration GAP8 is running [a] 3 Layer Pyramidal Viola-Jones Face Detection Algorithm,” the company explains. “The hardware required for the demo includes a GAPuino board, a QVGA Image sensor, a 3.2” LCD Screen and a 12V battery pack. All enclosed in a 3D printed case.
“As can be seen in the video, GAP8 can reliably detect faces. GAP8 can process a maximum of 70 fps [frames per second], with its fabric controller clocked at 250MHz and cluster at 175MHz. In its best power per frame configuration, when GAP8 detects a face it operates with a power consumption of just 0.80mW per frame per second. If no face is present the consumption drops to 0.35mW per frame per second.”
The demonstration video is available on YouTube, while more information on the GAPuino board can be found on the official website.
TinyFPGA BX Users Work on FPGA-Powered Console, Games
TinyFPGA creator Luke Valenty has called for contributors to submit entries to a project which aims to develop games running on a TinyFPGA BX-based handheld device dubbed the Field-Programmable Game Console (FPGC).
“Want to do something more playful,” Valenty posted to social networking site Twitter. “Join the community project to build a portable game console based on the TinyFPGA BX!”
Initially organised in September as the BX Portable Game Console project and tracked via the TinyFPGA Discourse forum, initial games included Asteroids and Pac-Man. In a spin-off from the original forum thread, developer Lawrie Griffiths launched an effort to port Atari 2600 titles to the device’s TinyFPGA BX driving hardware and 320x192 LCD display, publishing ports of Adventure, Pitfall, and the development of a Television Interface Adaptor (TIA) which core provided him with the ability to port Pong.
Those interested in contributing to the project can find more information on the TinyFPGA Discourse forum.
An FPGA Power Supply with Minimal Analogue Circuitry
The EDN Network has published a guide by Vardan Antonyan on the creation of a power supply using an FPGA and minimal analogue circuitry, both as a means of using spare resources for simpler circuits and “who can resist building your own power supply from scratch?
“Using FPGAs to design power supplies is overkill,” Antonyan admits, “unless you are using it for educational purposes. But if you have some portion of an FPGA left over to perform some useful function, it is practically free, and you can use the most expensive FPGA for this task without any guilt.
“By no means does this article claim to be the definitive answer to all power supply designs. The subject of power supply design is so broad that there are books written on the subject. This article will get you going with a minimalist/simple approach to switching power supply design and describes several methods of generating power by utilising FPGA resources and minimal analogue circuitry.”
Antonyan’s full guide can be found over on the EDN Network now.
FOSSi News In Brief
- “Important and Innovative” — Tom Verbeure on the VexRiscv Core
- Libre RISC-V M-Class CPU and 3D GPU Crowdfunding “Soon”
- “Weekend Fun” — David Shah adding Timing-Driven Detail Placement Algorithm to Nextpnr
- Adam Taylor on Implementing MIPI CSI-2 in an FPGA
- Enthusiast Outlet Linus Tech Tips Publishing “Design Your Own CPU” Video with SiFive
- EE News Europe: “OpenCores Rides Again in the RISC-V Era”
- OnChip Publishes “Bird’s Eye” Zoom Animation of New Microcontroller Board
- “How Best Should I Use the VGA Port?” — Dan Gisselquist on Building a Video Controller
- Hackaday: “FPGA Testbenches Made Easier”
- “Verifying a RISC-V in 1 Page of Code” — Steve Hoover on WARP-V Verification
- Hackaday: “Ken Shirriff Explains His Technique for Reverse Engineering Silicon”
- Vienna RISC-V Meetup, January 2019