El Correo Libre Issue 11

The Year of Free and Open Source Silicon

We wish all our readers a happy new year, and we hope you had some relaxing holidays.

Looking back at 2018, it’s clear to see a further rise of Free and Open Source Silicon projects. We have, for example, seen many great things coming from the RISC-V ecosystem, as well as the SymbiFlow project, just to mention some of the most popular. Last year’s ORConf was another great success, and we were thrilled to host so many brilliant speakers and support this great community.

Despite all the great projects and events we’ve seen over the last few years, I am convinced that we have an even more fantastic year for the community ahead of us. The FOSSi Foundation currently has no fewer than three events in the pipeline that we are organising, and there have been many interesting announcements and projects already for this year — some of which we have assembled in this issue of the newsletter.

On another note, the FOSSi Foundation will again apply as an umbrella organisation in the Google Summer of Code programme. This programme provides a great opportunity for small projects to get students involved to help raise their visibility. We highly encourage you to get in touch with us if you run a project which could use a few helping hands — and who couldn’t?

So, let’s make 2019 the year of Free and Open Source Silicon!

-Stefan Wallentowitz, Director, Free and Open Source Silicon (FOSSi) Foundation

35c3 Presentations Outline Free and Open Source Silicon Progress

A series of presentations given at the 35th Chaos Communications Conference (35c3) late 2018 have now been made available on the official media site, including several of interest to those in the field of free and open source silicon.

Topics of interest during the event included an update on the LibreSilicon project, an effort to create a manufacturing back-end for free silicon designs, details the process towards the manufacture of a first test wafer at a 1µm process node — which, the project’s maintainers admit, “does not sounds very ambitious, [but] this process node is still quite well documented in text books, robust and 5 volt tolerant.”

Clifford Wolf was also in attendance offering an overview of the popular nextpnr free and open source place-and-route tool for field programmable gate array (FPGA) projects, having unveiled the Project IceStorm open-source end-to-end FPGA toolchain at the earlier 32c3 event.

Finally, Tim ‘mithro’ Ansell presented on the SymbiFlow project, “the ‘GCC of FPGAs’ — a fully open source toolchain supporting multiple FPGAs from different vendors, [and] allowing compilation from Verilog to bitstream without touching vendor provided tools.”

All presentation videos are available to download or stream now, in a variety of formats.

The Amp Hour on Open FPGA Toolchains

As well as a series of scheduled lectures, there were numerous attendees with opinions on free and open source FPGA toolchains at the 35c3 event — and The Amp Hour, a popular podcast for electronics enthusiasts, caught up with three of them.

In a special edition of the podcast recorded during the event, iCEBreaker creator Piotr Esden-Tempski, nextpnr’s Clifford Wolf, and Project IceStorm contributor David Shah discuss topics surrounding the creation of fully free and open source toolchains for FPGA development.

Items of interest discussed during the podcast include Synbiotic EDA, the iCEBreaker crowdfunding campaign, the Yosys tool set, nextpnr, and the talks given by Wolf and Tim Ansell during the event, along with a project to add a WS2812 controller to Wolf’s PicoRV RISC-V design.

The podcast is available to download now from the official website.

FOSDEM 2019 CAD and Open Hardware Devroom Schedule Published

The Free and Open source Software Developers’ European Meeting 2019 (FOSDEM 2019) is dedicating one of its developer rooms — ‘devrooms,’ in event parlance — to electronic design automation, and has published the schedule of talks that will take place there.

Dubbed the CAD and Open Hardware Devroom, the EDA-focused track will include talks from Felix Salfelder on the GNY Circuit Analysis Package Gnucap, Holger Vogt on the ngspice circuit simulator, David Shah on Project Trellis and nextpnr, Guillaume Delbergue on open-source virtual prototyping, Staf Verhaugen on the search for the ideal hardware description language for open silicon projects, Wayne Stambaugh on the status of the KiCad project, and more.

The full schedule can be found on the official website, while FOSDEM 2019 itself takes place in Brussels on the 2nd and 3rd of February.

iCEBreaker iCE40 FPGA Dev Board Crowdfunder Smashes Funding Goal

Piotr and Danika Esden-Tempski have successfully funded the open iCEBreaker iCE40 FPGA development board via Crowd Supply, raising more than three times the funds required to produce the device.

“Are you ready to venture into the brave new world of digital logic design,” the campaign description, aimed at those for whom open FPGA development is relatively new, asks. “The iCEBreaker FPGA board is specifically designed for you. It works out of the box with the latest open source FPGA development tools and next-generation open CPU architectures.

“The iCEBreaker is easily expandable through its Pmod connectors, so you can make use of a large selection of third-party Pmod modules, as well as the several new Pmods we’ve specifically designed for it. There’s ample documentation, including well-tested workshop curricula, video tutorials, and datasheets.”

The campaign remains open for the next three days, with iCEBreaker boards and accessories available to order via Crowd Supply.

OpTiMSoC Many-Core Framework 2018.1 Released

Free and Open Source Silicon Foundation director Philipp Wagner has announced the release of the Open Tiled Manycore System-on-Chip (OpTiMSoC) 2018.1 framework, bringing in a great deal of work to the project.

“It’s a major release containing two years of work,” Wagner explained in a pre-Christmas launch announcement, “including: much more reliable debug and off-chip connections, thanks to the work done by Max; a fully rewritten host debug software; a refactored NoC implementation; Linux support; many additional tests, including system tests running on the FPGA; build automation: all tests, including the FPGA tests, run every night; many, many fixes and improvements all over the code base.”

Full details on the improvements and changes can be found in the official launch announcement, while an explanation of the OpTiMSoC’s Linux support, including a video demonstration, is also available from the project website.

M-Labs Releases nMigen Python Toolbox for “Building Complex Digital Hardware”

Hong Kong-based M-Labs has published the source code for nMigen, a next-generation replacement for the Migen library which aims to give developers the “richness of the Python language” for hardware design.

“nMigen FHDL [is] a library that replaces the event-driven paradigm with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and most importantly allows the design’s logic to be constructed by a Python program,” its creators explain. “This last point enables hardware designers to take advantage of the richness of the Python language — object oriented programming, function parameters, generators, operator overloading, libraries, etc. — to build well organised, reusable and elegant designs.

“Other nMigen libraries are built on FHDL and provide various tools such as a system-on-chip interconnect infrastructure, a dataflow programming system, a more traditional high-level synthesiser that compiles Python routines into state machines with datapaths, and a simulator that allows test benches to be written in Python.”

The project is described as “incomplete and undergoes rapid development,” but its source is available under the BSD two-clause licence on GitHub now. Demonstrations of its use, meanwhile, can be found via Twitter.

Raspberry Pi Foundation Telegraphs RISC-V Interest, Open ISA Support

The Raspberry Pi Foundation, creator of the low-cost but proprietary Raspberry Pi family of single-board computers, has announced its interest in the RISC-V ecosystem with members of the RISC-V Foundation and a proposal to contribute to the software side of things.

In an interview with AB Open, co-founder Eben Upton explained: “This isn’t a product announcement. We believe that instruction-set diversity is important, that open, free instruction set architectures are an important enabler for innovation, and there’s a lot of exciting work going on in the RISC-V community at the moment.

“Our impression is that the hardware side of things is going pretty well. We think we can contribute on the software side, which is important if RISC-V is going to become a viable alternative for desktop general-purpose computing. By ‘software,’ we mean some subset of toolchain, kernel, userland, SIMD fastpaths, JITs, etc. We will be soliciting proposals for small projects in these areas.”

The Raspberry Pi Foundation, whose current products exclusively use the Arm instruction set architecture, joins the RISC-V Foundation as a Silver Member.

PULP Platform Announces Arnold Tape-Out, Combining PULPissimo and eFPGA

The Parallel Ultra-Low Power (PULP) Platform project has announced the tape-out of a new design, combining the PULPissimo RISC-V based microcontroller with an embedded field-programmable gate array (FPGA) from QuickLogic — and it’s named for a certain bodybuilder who can always be relied upon to be back.

“We have taped out Arnold,” the project announced via Twitter, “that combines our PULPissimo line of microcontrollers with an eFPGA from QuickLogic Corporation. The eFPGA can be programmed through the RI5CY core in the PULPissimo.”

The chip will be back form manufacturing, project maintainers have estimated, in around three to four months. In the meantime, more information is available from the IIS Chip Gallery, though the technical parameters in the table are said to be incorrect at the time of writing.

Wave Computing Announces Open MIPS Initiative

Wave Computing, which acquired the MIPS business from Imagination Technologies in June 2018, has announced it plans to make the instruction set architecture available free of charge with no licensing or royalty payments required.

“Having spent years in the open source technology movement, I can attest to the hunger for community-driven solutions,” says Art Swift, president of Wave Computing’s MIPS IP division. “However, until now, there has been a lack of open source access to true industry-standard, patent-protected, and silicon-proven RISC architectures. The overwhelmingly positive response we have received thus far from customers on our MIPS Open initiative is an indication of the dramatic, positive impact we believe the program will have on the industry. We invite the worldwide community to join us in this exciting journey and look forward to seeing the many MIPS-based innovations that result.”

“The MIPS Open initiative is a key part of Wave’s ‘AI for All’ vision,” adds Lee Flanagin, Wave’s senior vice president and chief business officer. “The MIPS-based solutions developed under MIPS Open will complement our existing and future MIPS IP cores that Wave will continue to create and license globally as part of our overall portfolio of systems, solutions, and IP. This will ensure current and new MIPS customers will have a broad array of solutions from which to choose for their SoC designs, and will also have access to a vibrant MIPS development community and ecosystem.”

Details of exactly how open MIPS Open truly is, including the licence under which the ISA and associated core implementations will be made available, have not yet been disclosed by the company.

RISC-V Summit Summarised while Videos, Slides are Published

RISC-V Foundation executive director Rick O’Connor has published a retrospective of the organisations first RISC-V summit, held in Santa Clara last year, while the first slides and video from the event have begun to appear on the official website.

“With more than 1,100 attendees from over 20 countries, the RISC-V Summit in Santa Clara was a true testament of the growth of the RISC-V ecosystem over the past year,” O’Connor writes. “More than double the size of the 7th RISC-V Workshop in Milpitas, the inaugural RISC-V Summit featured more than 50 presentations and 29 exhibitors discussing RISC-V implementations and how the RISC-V ISA will shape the industry for decades to come.

“Although the RISC-V Summit has ended, one thing is for certain — our ecosystem continues to grow and adoption is in full swing. We are excited to reconvene next year for an even bigger and better event. Mark your calendars for RISC-V Summit 2019, taking place Dec. 3–6, 2019 at the San Jose Convention Center.”

O’Connor’s full retrospective is available on the RISC-V Foundation website, while slide decks and video recordings are available on the RISC-V Summit Proceedings page.

FOSSi News In Brief

• Hackaday: “Open Source IDE for FPGAs as QtCreator Learns Verilog.”
• GNU Debugger (GDB) 8.2.1 brings RISC-V ELF support.
• HDLProject v1.1.1 adds syntax highlighting for VHDL, Verilog popups, and more.
• Drew DeVault: “Porting Alpine Linux to RISC-V.”
• Dan Gisselquist: “ZipCPU Highlights from 2018.”
• AB Open: “Thales, IIT Madras Partner for Fault-Tolerant SHAKTI RISC-V Processors.”
• Kevin Hubbard: “My new flagship DVI board for FPGAs.”
• Libre RISC-V M-Class project publishes an introduction to Simple-V.
• Whitequark: “I’ve redesigned the Boneless ISA, which is now simpler to decode, significantly more powerful, and has a ton of space to expand into.”
• EET India: “Krste Asanović — RISC-V Momentum is Massive in India.”

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