FOSSi Hits the Prime Time
Last week I visited a small RISC-V themed workshop in Munich, Germany — or so I thought. When I showed up there, a crowd of over 50 people from industry and academia was eager to hear what RISC-V is all about, and how open source offerings could make their lives easier. This clearly show that, even though FOSSi has been with us for a long time, it is now ready for prime time.
Companies are thinking hard about how they could replicate the success of open source software in the hardware domain. At the same time, academia is trying harder to make collaboration between partners seamless and increase the reproducibility of their research results. Having code available under a free and open licence is the first step towards that.
The Munich event confirmed it again: Conferences and workshops are a great venue to exchange ideas, and gain a better understanding of how FOSSi works. That’s why the FOSSi Foundation spends much time organising conferences, and the next one is just around the corner: in early May we will have Latch-Up, our first ORConf-like event in Northern America!
If you want to move from learning to doing and are a student, I highly recommend to have a look at the Google Summer of Code projects of the FOSSi Foundation. They offer a fully-funded opportunity to work on a relevant open source project, helped by an experienced mentor.
I hope you enjoy this edition of El Correo Libre, and please get in touch with us with any feedback!
-Philipp Wagner, Director, Free and Open Source Silicon (FOSSi) Foundation
FOSSi Foundation Selected as Google Summer of Code Mentor Organisation
The Free and Open Source Silicon (FOSSi) Foundation has again been selected to serve as a mentor organisation in the Google Summer of Code (GSOC) programme, providing students with support and a financial stipend for their contributions to a range of open source projects in the field.
“Google Summer of Code is an excellent programme for students to get a stipend by Google to work on open source projects,” explains Foundation director Olof Kindgren. “To start things off, we have prepared a list of project ideas. As a student your job is to write a realistic project proposal to show us that you have a good idea of the work involved, and discuss the idea with us to get feedback. Our job is to match you up with a suitable mentor.
“As there are more student proposals than we have seats, a well-written project idea is important for us to judge whether we should choose you over someone else. It is also a good idea to get involved with the community early on to get a better feeling for what kind of project you want to do, and what already exists.”
A non-exhaustive list of suggested project ideas has been published on the FOSSi Foundation website, while interested parties can get in touch via email on email@example.com.
Linux Foundation Launches CHIPS Alliance Project
The Linux Foundation has announced the formation of a new project, the CHIPS Alliance, to focus on free and open source silicon, boasting as its founding members Western Digital, SiFive, Esperanto Technologies, and Google.
“This serves as further proof that FOSSi is here to stay and that the industry has taken notice,” says FOSSi Foundation director Stefan Wallentowitz. “We look forward to working towards the same goal of Free and Open Source Silicon.”
“Open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards,” explains Mike Dolan, vice president of strategic programs at the Linux Foundation, of the reason for its expansion into free and open source silicon. “The same collaboration model applies to the hardware in a system, just as it does to software components. We are eager to host the CHIPS Alliance and invite more organisations to join the initiative to help propel collaborative innovation within the CPU and SoC markets.”
“As new workloads surface every day, we need new silicon designs in order to optimise processing requirements,” adds Martin Fink, interim chief executive of the RISC-V Foundation and executive vice president and CTO of Western Digital. “Today’s legacy general purpose architectures are, in some cases, decades old. With the creation of the CHIPS Alliance, we are expecting to fast-track silicon innovation through the open source community.”
Western Digital has confirmed it is to contribute its 32-bit RISC-V-based SweRV core, test bench, and ISA simulator, SiFive its RocketChip SoC generator, Diplomacy SoC parameter negotiation framework, and TileLink interconnect fabric while also contributing to the continued development of the Chisel hardware description language and FIRRTL intermediate representation specification and transformation toolkit, while Google is to contribute a Universal Verification Methodology (UVM) instruction stream generator for RISC-V cores.
More information is available on the official website.
Fomu FPGA Mini Development Board Gets FOSSi USB Stack for RISC-V Core Comms
The Tomu FPGA miniaturised development board detailed back in ECL Issue 9, more commonly known as Fomu, has received a free and open source USB stack offering full interaction with the on-board RISC-V soft core.
Based on the Lattice iCE40UP5K, with 5,000 lookup tables (LUTs), digital signal processing (DPS) tiles, 128kB RAM, and 1,024kB flash, the Fomu is loosely based on the earlier hand-soldered Tomu design and fits entirely inside a standard USB Type-A port.
“Thanks to a lot of hard work, and a very helpful patch from tnt in the #tomu [IRC] channel,” the Tomu team explain via the project’s official Twitter account, “the USB stack is now producing reliable traffic and interacting with the RISC-V soft core!”
The Fomu board was successfully funded on Crowd Supply earlier this year, and shipping of the Fomu Engineering Validation Test (EVT) board variant began in mid-February with validated boards scheduled for late June.
FOSSi Foundation Announces May Latch-Up Conference in Portland, Oregon
The FOSSi Foundation has announced a new conference dedicated to free and open source silicon, Latch-Up, to be held in early May in Portland, Oregon.
“Latch-Up opens a new chapter for the FOSSi Foundation, with it being the first event in the spirit of ORConf held in North America,” explains Foundation director Olof Kindgren of the event, named for a short in a circuit. “Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a wide range of topics: open source IP blocks and SoCs, open source simulators, compilers, synthesis, and physical implementation tools for both FPGA and ASIC.
“Latch-Up aims to bring together the North American open source digital design community for an event in the mould of ORConf — the FOSSi Foundation’s annual European community conference. Like ORConf, Latch-Up will be will be free to attend and consist of a relaxed format of presentations and discussions throughout a weekend, with plenty of time for networking. A dinner on the Saturday evening will be arranged and all attendees are invited to attend.”
A call for presenters has been issued, with interested parties asked to fill in the proposal form. More information is available from the official website, and while tickets are free registration is required.
The first Latch-Up is scheduled for the weekend of the 4th-5th of May 2019.
FuseSoC Version 1.9.1 Released, Brings Improved Sphinx-Generated Documentation
Developer and FOSSi Foundation director Olof Kindgren has announced the release of FuseSoC 1.9.1, the latest version of the popular hardware definition language (HDL) project package manager and build tool collection.
“Following the good example of other FOSSi devs,” Olof writes in his Twitter announcement, “I’m taking the opportunity today to release version 1.9.1 of FuseSoC. A ‘position’ argument to generators and Sphinx docs would be the noteworthy changes this time.”
The new release sees improved documentation, generated using the Sphinx utility, made available via Read The Docs as a means of improving the tool’s accessibility to new users and easing reference for existing users.
More information on FuseSoC itself, including installation instructions, can be found on the project’s GitHub repository.
Project Trellis Receives First Stable Release
Developer David Shah has announced the first stable release of Project Trellis, an effort to fully document the Lattice Semiconductor ECP5 bitstream format.
“I’ve just made the first stable release of Project Trellis,” David announced via Twitter late February. “Hopefully this is helpful to those interested in packaging for distros, apio, etc.”
The first stable release includes what David describes as “a reasonable set of ECP5 data and supporting code,” including all logic tile functionality and routing, the majority of IO and IOLOGIC routing and configuration, all block RAM routing and configuration, global clock routing, phase-linked loops (PLLs), clock dividers, the internal oscillator, “other misc. blocks,” and tools for packing and unpacking bitstreams.
At the same time, developer Luke Valenty has suggested ways that people can contribute to the project. “Want to contribute to the open FPGA movement,” Luke asks via Twitter. “Project Trellis has a few enhancements that are perfect for a newcomer to tackle. For example, you could implement bitstream compression for ECP5 FPGAs.
“There are a few other bitstream enhancements available to implement. These enhancements will enable faster programming and boot times for ECP5 FPGAs using bitstreams generates by the open source tool chain. A faster development loop means it’s easier for newcomers to learn and for experts to innovate!”
More information, alongside the source code under a permissive ISC Licence, is available from the Project Trellis GitHub repository.
David Shah Demonstrates ECP5 Versa Yosys, Nextpnr, Trellis Workflow
Fresh from announcing the first stable release of Project Trellis, David Shah has demonstrated how it can be used in a workflow alongside Yosys and nextpnr to build systems-on-chip (SoCs) for the Lattice Semiconductor ECP5 Versa FPGA development board.
“Yosys, nextpnr & Trellis can now build an Enjoy-Digital LiteX SoC for the ECP5 Versa” David writes on Twitter, “with DDR3 memory and Gigabit Ethernet — capable of booting via TFTP! Total build time is just 1m45s with the new placer, resource utilisation 32% so plenty of room for ‘extras’ too.”
Imagery of the boot sequence and the development board itself can be found on David’s Twitter post.
AB Open Showcases RISC-V Based Desktop PC Build
AB Open’s Andrew Back, who serves as the FOSSi Foundation treasurer, has demonstrated how close free and open source silicon is coming to being an off-the-shelf, commoditised, mainstream technology by building a RISC-V desktop running GNU/Linux.
“While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, for e.g. IoT and edge processing — one question that people cannot help but ask is, so when can I have a RISC-V PC,” Andrew writes by way of introduction to the project. “The answer to which is, right now.”
Andrew’s build takes a SiFive HiFive Unleashed development board, a Microsemi HiFive Unleashed Expansion Board, and miscellaneous components including an off-the-shelf graphics card and storage, and puts them together in a custom-built actively-cooled chassis. Using a port of Fedora Linux developed by Western Digital’s Atish Patra, the result is a fully-functional RISC-V desktop.
“This is obviously not exactly commodity hardware,” Andrew admits, “but it does show that the ingredients are there and the combination provides a powerful development platform for anyone who might want to prototype a RISC-V PC — or indeed a vast array of other applications which stand to benefit from the open ISA.”
More details on the build, and a supporting video, are available on the AB Open website.
Will Green, Michael Field Launch Free FPGA Display Implementations
Anyone looking to get a video output from an FPGA now has two new free options to investigate: Will Green’s Project F Display Controller and Michael Field’s DisplayPort-Verilog.
“Just finished first version of my FPGA display controller.” Will writes of Project F’s new Display Controller on Twitter. “Easily adds graphics to FPGA projects with VGA, DVI, or HDMI. It can generate TMDS or use @bml_khubbard DVI Pmods. Detailed guide forthcoming; in the meantime constructive feedback is sought.”
“I’ve uploaded my IP-free Verilog FPGA DisplayPort Implementation to a new GitHub repo,” writes Michael of his own offering. “Feel free to take a look around, and try it on your board. My Verilog skills are weak, so any help would be greatly received.”
The Project F Display Controller is available on the Project F GitHub repository under an MIT Licence; DisplayPort_Verilog is published under the same licence, in what is described as a “very alpha” state, on Michael’s GitHub repository.
Amazon Announces RISC-V Support in the FreeRTOS Kernel
Amazon’s Jeff Barr has announced the addition of support for the free and open RISC-V instruction set architecture (ISA) to the FreeRTOS kernel, targeting embedded and Internet of Things (IoT) implementations.
“RISC-V is a free and open ISA that was designed to be simple, extensible, and easy to implement. The simplicity of the RISC-V model, coupled with its permissive BSD licence, makes it ideal for a wide variety of processors, including low-cost microcontrollers that can be manufactured without incurring license costs,” Jeff writes. “The RISC-V model can be implemented in many different ways. Development tools, including simulators, compilers, and debuggers, are also available.
“Today I am happy to announce that we are now providing RISC-V support in the FreeRTOS kernel. The kernel supports the RISC-V I profile (RV32I and RV64I) and can be extended to support any RISC-V microcontroller. It includes preconfigured examples for the OpenISA VEGAboard, QEMU emulator for SiFive’s HiFive board, and Antmicro’s Renode emulator for the Microchip M2GL025 Creative Board.”
Full details are available in the official announcement.
Debugging the OpenISA Vega Development Board with Eclipse, MCUXpresso
MCU on Eclipse’s Erich Styger has been experimenting with the OpenISA Vega development board, distributed in limited numbers to interested US developers late last year, and has written of how he has integrated it into his debugging workflow.
“There was an offer for a free board for which I applied,” writes Erich in the piece, which includes full instructions on setting up a development and debug environment for the board. “I nearly have forgotten about this, but after several weeks afterwards I received two boards. The board is interesting too. It looks like one of the normal [NXP] ‘Freedom’ boards on steroids. The board comes with a USB cable, five jumpers and a short ‘getting started’ leaflet.
“Using a RISC-V core or as in this case using multiple ones is fun, and I’m glad to see that software and tools are evolving,” Erich concludes.
The full piece is available on MCU on Eclipse.
FOSSi News In Brief
- Clifford Wolf: Yosys receives “some support” for inference of iCE40 DSP cells.
- David Shah “working on adding support for derived timing constraints to nextpnr-ecp5.”
- Dan Gisselquist on “using sequence properties to verify a serial port transmitter.”
- Electronics Point: “RISC-V’s Ted Marena Discusses His Career and the Benefits of an Open [Instruction] Set Architecture.”
- Seeed Studio launches Sipeed Tang Primer FPGA development board, also teases RISC-V AI “HAT” for Raspberry Pi.
- Elektroniktidningen: “Fault Tolerant RISC-V from Gothenburg” (English translation.)
- Third Workshop on Computer Architecture Research with RISC-V (CARR-V) launches Call for Papers.
- Semiconductor Engineering: “The Challenge of RISC-V Compliance.”
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