El Correo Libre Issue 14

Published in

LibreCores

12 min readApr 9, 2019

Healthy Signs for the Free and Open Source Silicon Movement

I really feel like the whole Free and Open Source Silicon movement has finally taken off. Many from our community have been around for ten years or more, but only over the last few years have we really seen a steadily increasing interest in open silicon design and engineering design automation tools. Many awesome projects are becoming very popular and attracting new folks, and we are seeing many companies, large enterprises, smaller companies and startups, becoming increasingly interested and invested in the ecosystem.

It is also a healthy sign that we have recently seen new foundations rising. While we are historically a little bit anxious about fragmentation, thinking back to the many painful years experienced by the OpenCores community, we believe that new players such as the CHIPS Alliance and the Free Silicon Foundation complement our activities well. We are also aware of a few other new foundations that will go public over the next couple of months. We are very optimistic that we can all find our part of the ecosystem and cooperatively help to nurture future awesome projects!

The FOSSi Foundation traditionally wants to bring the entire community together, from big industry players and startups to academia and hobbyists. As such, we think that our activities in LibreCores and our organisation of three free-to-attend community events with around 100 attendees each this year alone are of value to the community and help define our spot in the expanding landscape of foundations very well.

We are looking forward to meeting you all soon at our events in Portland (Latch-Up) and Zurich (WOSH)!

-Stefan Wallentowitz, Director, Free and Open Source Silicon (FOSSi) Foundation

Survey Highlights Popularity of Permissive Free and Open Source Silicon Licences

Moorcrofts LLP partner Andrew Katz has published a paper based on a survey into free and open source silicon licensing with a focus on processor cores, including input from FOSSi Foundation director Julius Baxter and treasurer Andrew Back.

“All interviewees believed that the most commercially effective open hardware core designs were those which adopted permissive licences,” Andrew’s paper, which is based on a survey commissioned by Western Digital in spring 2018 ahead of the release of its own RISC-V-based SweRV Core, explains. “The prevalence of these licences is borne out by desktop research.

“The stated various reasons for this are: that the currently available copyleft open hardware licences are insufficiently clear in their effect to be safely used; that the potential benefits of copyleft licensing in core designs are not yet sufficiently clear to show an overwhelming need to shift to a copyleft model; that copyleft licensing is certainly interesting and may have a place as the market matures. No interviewee was against copyleft core licensing in principle (although there was consensus that a weak copyleft with clearly defined boundaries was more likely to be commercially successful).”

The report, which includes a number of industry experts among its contributors, also highlights the popularity of the RISC-V instruction set architecture (ISA) specifically — though does not conclude whether this is “an artefact of the relatively small sample size and a shared familiarity by the interviewees with RISC-V [or] reflect a reality that RISC-V is the most prominent and widely adopted open ISA currently in use.”

The survey is available for free download now in the journal International Free and Open Source Software Law Review Volume 10, Number 1.

David Shah Demonstrates Open Source FPGA Inception

Developer David Shah has demonstrated a toolchain running on an open core itself created using an open toolchain — effectively creating a system which was open all the way down to its origin.

Demonstrated late last month during an event at the British Computing Society (BCS) in London, Rob Taylor described David’s creation thusly on his Twitter account: “Amazing seeing [David Shah] demo a full open source FPGA toolchain, running on a Linux on RISC-V on FPGA, created with an open source FPGA toolchain.”

The demo showcased a number of layers of openness at once: the original toolchain David used to create the demo was itself open, and used to create an open core based on the open RISC-V implementation on the FPGA; this was then used to execute a Linux-based operating system, on which the open toolchain itself was loaded — giving the platform the ability to generate more open cores itself.

The demonstration has been likened to the film Inception, in which the lead characters venture deeper into the layers of another character’s mind in order to implant a core idea — in this case the idea seemingly being “open is good.”

Miodrag Milanovic Announces Docker Open FPGA Toolchain Bundle

Developer Miodrag Milanovic has announced the release of Docker images and compilation scripts packaging the latest releases of a range of open source FPGA tools including Yosys, nextpnr, and Icarus Verilog.

“Have a need for latest builds of open source FPGA tools like yosys, nextpnr, iverilog and others,” Miodrag asks via his Twitter account. “Check here for docker images and scripts for building static binaries for your system. Supporting various OS and CPUs (like intel, arm, mips, or1k,…)

“Note that packages created are meant to be used with APIO, but still you can just place them in your PATH and use them directly. Easy way to cross compile for Raspbery-Pi, Ci-20 and similar SBC Linux machines. Builds for nextpnr are minimal and without GUI or python, so are usable on all systems.”

The Docker images and scripts are available to download now from Miodrag’s GitHub repository.

RISC-V Foundation Calls for Feedback on the RISC-V Formal Specifications

The RISC-V Foundation has announced draft Formal Specifications for the open RISC-V instruction set architecture, and is inviting members of the community to submit feedback ahead of the selection of a single specification.

“We are interested in your opinions on how useful you would find each of the approaches represented,” says Rishiyur Nikhil, chair of the ISA Formal Spec Technical Group at the RISC-V Foundation, of the drafts. “To date, these have been developed by various subgroups, each for their own purposes and with their own priorities.

“There are two ways to provide feedback: a short, structured questionnaire (should not take more than a few minutes); if you wish, you can provide more expansive free-form comments using the Issues tab of the GitHub repo.

“At the end of the feedback period, the ISA Formal Spec Technical Group will respond to each issue raised, and will make a recommendation to the RISC-V Foundation about which of the five specs should be adopted as the ‘official’ spec. An immediate use of the formal spec is to be the Golden Reference Model against which ‘Compliance’ is measured by the RISC-V Foundation. Over time, the spec is expected to be maintained and to grow to include future official features/extensions of the RISC-V ISA.”

The drafts, in Markdown format, along with instructions on accessing the feedback questionnaire, can be found on the RISC-V Foundation GitHub repository. Interested parties have until the 13th of May to submit their feedback.

Gisselquist Technology Releases ArrowZip, QSPI Flash Controller

Dan Gisselquist has announced the release of two new creations: a variant of the ZipCPU designed for the Trenz Max-1000 low-cost FPGA development board, dubbed the ArrowZip for the board’s US distributor Arrow, and a universal QSPI flash controller.

“For $30, the Max-1000 board is a nice entry board for beginners,” Dan writes, “once you get past the difficulty associated with building and loading a design onto the board, and once you get past the difficulty of getting an SDRAM controller to work on the board.

“For all of these reasons and more, I thought it might be a fun board to build a demonstration design with. Better yet, as of last week, the design appears to be working! Yes, working: flash controller, SDRAM controller, and indeed everything but the accelerometer.”

Shortly after, Dan also released a universal QSPI flash controller which comes with a detailed blog post on its creation. “The question before me, though, was whether it might be possible to build a single Quad-SPI controller that I could re-use with any flash device I came across,” Dan explains. “This blog article is about the design and verification of that new Quad-SPI flash controller.”

More information on the ArrowZip ZipCPU and the Universal QSPI Controller can be found on their respective blog posts.

OpenPiton r11 Available Now, OpenPiton+Ariane Boots SMP Linux

Jonathan Balkind has announced the release of OpenPiton 19–03–19-r11, also known as Release 11, which combines with the PULP Platform’s Ariane to boot symmetric multi-processing (SMP) Linux on an FPGA for the first time.

“In conjunction with the PULP Platform’s Ariane release 4.1, OpenPiton+Ariane boots SMP Linux on FPGA,” Jonathan explains. “This makes OpenPiton+Ariane the first Linux-booting, open-source, RISC-V system that scales from single-core to manycore.

“You can download our 1-core (Nexys Video Artix-7), 2-core (Genesys2 Kintex-7), and 4-core (VC707 Virtex-7) FPGA bitfiles today to try this out. We are actively working on adding support for the Ariane Floating-Point Unit and improving the stability of the system, but we are excited to share this significant early milestone as a teaser of what’s to come. Our existing Piton and Ariane chips provide us a mature base for future OpenPiton+Ariane implementations in silicon.”

The new release also includes the first support for simulating OpenPiton in Verilator, which becomes the fifth simulation platform for the design. “This new support is also under active development,” Jonathan continues, “with the intent to provide a fast, open-source simulation infrastructure.”

More details are available on the official website, along with a link to download the new release.

Calista Redmond Outlines “Key Priorities for Accelerating the RISC-V Revolution”

Newly-appointed chief executive of the RISC-V Foundation Calista Redmond has penned an article outlining her organisations key priorities for accelerating the adoption and deployment of its eponymous open instruction set architecture.

“With the significant uptick in RISC-V adoption over the past few years, the RISC-V Foundation Technical Committee has made it a priority to prepare the RISC-V base ISA and standard extensions for ratification,” explains Calista. “There are already a wide variety of RISC-V implementations in industry and academia, designed into applications including graphics engines, machine learning and AI, networking, storage, security, embedded and general purpose processors.

“The RISC-V community has now formally agreed on an ISA standard and frozen the ISA, guaranteeing compatibility. This means that software written for RISC-V will run on all similar RISC-V cores forever giving hardware engineers increased flexibility over processor implementation. The RISC-V community has also been hard at work developing a RISC-V compliance framework. This framework tests whether a processor under development meets the open RISC-V standards, which is critically important for companies implementing RISC-V cores in their products.

Concluding with a message of thanks to everyone in the RISC-V community, Calista requests feedback and input both formally via Task Groups and informally. More information is available in the blog post.

Microsoft Releases Project Zipline Hardware-Implementable Compression Algorithm

Azure, the cloud computing division of software giant Microsoft, has released a hardware-implementable compression algorithm aimed at large data sets: Project Zipline.

“Microsoft’s Project Zipline compression algorithm yields dramatically better results, up to 2X high compression ratios versus the commonly used Zlib-L4 64KB model,” says Microsoft’s Kushagra Vaid of his team’s creation. “Enhancements like this can lead to direct customer benefits in the potential for cost savings, for instance, and indirectly, access to petabytes or exabytes of capacity in a cost-effective way could enable new scenarios for our customers.

“We are open sourcing Project Zipline compression algorithms, hardware design specifications, and Verilog source code for register transfer language (RTL) with initial content available today and more coming soon. This contribution will provide collateral for integration into a variety of silicon components (e.g. edge devices, networking, offload accelerators etc.) across the industry for this new high-performance compression standard.

“Contributing RTL at this level of detail as open source to OCP [the Open Compute Project] is industry leading,” Kushagra continues. “It sets a new precedent for driving frictionless collaboration in the OCP ecosystem for new technologies and opening the doors for hardware innovation at the silicon level.”

Released under the permissive MIT Licence, Project Zipline is available now — including its RTL implementation — on the Open Compute Project’s GitHub repository.

Nextpnr Gets HeAP Analytic Placer, Dramatic Performance Boost

The open FPGA place and route tool nextpnr has received official support for a next-generation analytic placer dubbed HeAP, promising significant performance and quality of result (QoR) gains for supported FPGA platforms.

“The HeAP analytic placer has now hit nextpnr upstream,” David Shah announced via Twitter late last month. “Enabled by default for ECP5, use ` — placer heap` for iCE40. Should give significant runtime improvements for bigger designs. There is a notable QoR improvement for ECP5, due to better handling of rel. constraints (heavily used for muxes and DRAMs) and the larger device. For iCE40 the main improvement is switching to criticality based timing weighting, which applies to SA too now. The improvement in both cases works out to be in the 10–30% range, heavily design dependent though (as always).”

Asked why the new placer isn’t enabled by default for iCE40, David replied: “Really just needs a bit more testing with real world use cases, should be iCE40 default in a month or two. It’s default for ECP5 already because the runtime difference is so big — 10x+ for large designs — so it’s worth any small risk (SA still an option as fallback).”

The latest nextpnr release can be found on the official GitHub repository.

An Annotated Deep Dive into Western Digital’s SweRV Core

Tom Verbeure has published an annotated deep-dive into Western Digital’s recently released SweRV Core, based on the open RISC-V instruction set architecture, using the materials and details the company has released thus far.

“To satisfy the true geeks, Western Digital organized a SweRV Deep Dive at the Bay Area RISC-V Meetup,” Tom explains. “The meetup was well organized (free food!) and attended by roughly 100 people. Zvonimir Bandic, Senior Director of Next Generation Platform Technologies Department at Western Digital, gave an excellent presentation, well paced, little marketing fluff, with sufficient technical detail to pique my interest to dive deeper in the specifics of the core.”

Tom’s blog post goes through Zvonimir’s presentation, adding additional details provided during the meet-up and gleaned from the SweRV sources available on GitHub and the supporting programmer’s reference guide.

Tom’s conclusion, however, is one that suggests SweRV will be of use only at the professional end of the market: “I’m still in the early stages of going through the SweRV RTL and ISS, but it’s clear that SweRV is not a good fit to stick in an FPGA for hobby projects,” he explains, highlighting issues like a wasteful register file, slow clock speed when implemented on an FPGA, RTL written in SystemVerilog with constructs not yet supported in Yosys, and an overall size that precludes the use of smaller, cheaper, hobbyist-friendly FPGA parts.

The full deep-dive is available now on Tom’s blog alongside a copy of the original slide deck.