El Correo Libre Issue 15

Published in

LibreCores

11 min readMay 15, 2019

Catch-Up and Latch-Up: FOSSi Foundation’s First US Multi-Day Event

Latch-Up in Portland, Oregon last weekend marked the first multi-day FOSSi Foundation event we’ve held outside Europe. What transpired surpassed even our best expectations. We cannot thank everyone involved enough, and it’ll be difficult for this write-up to do justice to the quality of the presenters and the enthusiasm for open source hardware in the room and, later, in the bars of Portland.

A soft opening to the weekend came in the form of a hackfest for the TimVideos project hosted by Jon Hannis and the crew at Ctrl-H, the PDX Hackerspace. With such a cool venue and a great backyard for a barbecue, plenty of folks came along with most rolling up the sleeves for some tutorial action. A big thanks again to Ctrl-H for hosting us.

Our venue for the weekend was over in South East Portland: Revolution Hall is an old school building, abandoned for 20 years until a recent rejuvenation project turned it into a multi-use venue. It was the perfect site for the 70-odd folks who joined us each day for talks, demos, and, in between those, a bit of exploring the neighbourhood’s eateries and bars.

We had a great set of presenters who shared their work and ideas throughout the weekend. Some personal highlights were hearing Mr WaveDrom himself, Aliaksei Chapyzhenka, talk about the usefulness of diagrams in engineering, Josh Wise’s experience open sourcing a major piece of IP at a semi company, hearing about the Nyuzi open-source GPGPU from Jeff Bush, and Piotr Esden-Tempski’s impassioned call to arms for open source FPGA tooling.

Two talks, though, stand out for me, as they demonstrated that youth and perceived inexperience are no barrier to getting into open source engineering. These were Wenting Zhang’s talk on building an entire Game Boy system emulator on an FPGA, and Cole Johnson’s reverse engineering and reanimation of a Pong-playing chip from the 70s. Both floored the audience with details of their accomplishments. Please check our their (and everyone else’s!) talks on the FOSSi Foundation’s YouTube channel.

As we do each year at ORConf — Latch-Up’s European sister conference — we held the traditional conference dinner on the Saturday night. It provided a relaxed few hours for everyone to enjoy some food in Portland’s Old Town. Thanks again to SiFive for sponsoring the evening.

We were very pleased to see a mix of hobbyists, professionals, and plenty of curious folks come along and share their work and experiences whether over the microphone or over a coffee. We were also pleased to welcome plenty of people from the local tech scene, aka the Silicon Forest; it was great to meet you all and we hope to have inspired some of you to engage open source projects through your work.

As much as the event went seamlessly for us, we were more pleased with how engaged everyone seemed to be with each other during the breaks. This is a large part of the reason we run these events. Also thanks to all who brought along hardware and gave us a close-up view of their wares.

We’d like to thank the folks who sponsored us this year at Latch-Up: SiFive, Mentor, and Crowd Supply, as well as those of you who purchased professional tickets to join — we can’t do this without your support. Carl and the Next Day Video team also did a stellar job (same day video, in fact!) and we hope everyone enjoys the videos of the talks. And, of course, a final thanks again to everyone who joined.

This was a bit of a trial run for us in the US, and we’re very happy with the result. By the end of the weekend we were already being asked where we’d run the next one, so I guess that settles it: there will be a Latch-Up 2020, folks. If you can’t wait that long, there’s always WOSH in Zurich in June and ORConf in Bordeaux in September. We hope to see everyone again at one of our events or, as always, catch up and Latch-Up.

-Julius Baxter, Director, Free and Open Source Silicon (FOSSi) Foundation

Image courtesy of Monica Houston

Research Project Uses RISC-V Base for Allegedly “Unhackable” Processor

A research project at the University of Michigan has spawned a new processor, Morpheus, which its creators claim to be “unhackable” — and, as you might expect, they used a free and open source silicon instruction set architecture as the basis for the project.

“Today’s approach of eliminating security bugs one by one is a losing game,” claims Todd Austin, professor of computer science and engineering at the University of Michigan and one of the developers of the chip. “People are constantly writing code, and as long as there is new code, there will be new bugs and security vulnerabilities.

“Imagine trying to solve a Rubik’s Cube that rearranges itself every time you blink. That’s what hackers are up against with Morpheus. It makes the computer an unsolvable puzzle.”

Based on the RISC-V ISA, Morpheus works by encrypting and relocating code and data 20 times per second — increasing that rate if a built-in watchdog detects an attack — with, its creators say, around a one percent impact to operational performance.

The team’s work is available in the paper Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defences with Churn (PDF warning).

Western Digital Releases FPGA SweRV Core Reference Platform

Martin Fink, chief technology officer of storage giant Western Digital, has spoken of the “gratifying response” to the company’s release of its in-house RISC-V processor implementation, the SweRV Core, and has overseen the provision of a new reference platform for use with Xilinx FPGAs.

“Western Digital is pleased to provide the SweRV Core to the open source community. The initial response and targeted uses are gratifying to the entire development team and all of Western Digital,” says Martin of the response the company has seen. “We look forward to the acceleration of the RISC-V ecosystem and the innovations which will result from this core.”

The new SweRV Core reference platform targets implementation on a Xilinx FPGA, and the company claims it is “production grade” and ready for commercial use. The released project, made available under the Apache 2.0 licence, targets the Digilent Nexys4 DDR FPGA development board, and comes with example software and support files.

Full details are available on the project’s GitHub repository.

Gentoo Linux Announces Experimental Support for RISC-V

The Gentoo Linux distribution, which compiles all software from source on the user’s machine in order to boost performance and compatibility, has announced “experimental” support for the open RISC-V instruction set architecture.

“After some preparations, we’re happy to announce (initially experimental) support for a new arch,” writes Andreas Huettel on the project mailing list. “The keyword is ‘~riscv’; no stable keyword will be used in the beginning.”

The RISC-V Architecture Support Project aims, its organisers explain, to bring first-class support for RISC-V CPUs to Gentoo — though plenty of work still remains before that will be the case.

Full details are available on the Gentoo Linux wiki.

SIWA: Costa Rica’s First Native Processor for Medical Applications

The DCI Lab of the Electronic Engineering School at the Technological Institute of Costa Rica (TEC) has announced the development of the country’s first native processor, dubbed SIWA (“ancestral wisdom” in the Cabécar language), for use in medical equipment — and it’s based on an open instruction set architecture.

Based on a 32-bit variant of RISC-V, the microcontroller has been implemented on a 180nm CMOS semiconductor node and has been trialled in medical devices including a cardiac stimulator. Its creators have suggested that successor designs will be less focused on the medical field, with variants for industrial automation and computer vision projects.

“This milestone not only proves the existence in Costa Rica of the necessary technological capacity to initiate joint developments in the microcircuits area with the country’s high-tech industry,” claims Alfonso Chacón of the TEC Electronic Engineering School, “but also lays the foundation for a national microelectronics industry.”

Thus far, TEC has not publicly released any source files or licensing information for SIWA.

64-bit “Simba” Processor, Sri Lanka’s First, Successfully Boots Linux

Vithurson Subasharan has announced the first successful boot of Linux on Simba, a 64-bit RISC-V IMA processor written in Verilog — claimed to be Sri Lanka’s first native processor design.

“‘Simba’ a RISC-V 64 IMA based an implementation written in Verilog finally boots Linux,” Vithurson wrote in a thread on the RISC-V hardware developers mailing list. “Thanks everyone for being helpful in understanding related things. It’s 40MHz, but [we’re] hoping to push it above 100 on ZedBoard.”

A video of the boot process has been published as part of the thread, but no public documentation has yet been made available.

QEMU 4.0.0 Brings Broader Support for Emulating Free and Open Source Silicon Platforms

Version 4.0.0 of the QEMU emulator has officially launched, adding in a range of new features designed for free and open source silicon enthusiasts — particularly those working with the RISC-V instruction set architecture.

In version 4.0.0, QEMU adds support for the Peripheral Component Interconnect (PCI) and Universal Serial Bus (USB) buses on the ‘virt board’ virtual development board, greatly broadening the designs which can be tested in emulation. For those working on SiFive IP, the SiFive_u virtual machine now includes support for symmetric multi-processing (SMP) while the SiFive UART adds support for transmission interrupts.

More generally, there have been a range of bug fixes and improvements which have seen additional fields added to mstatus, three states for the FS field, support for writing to the misa CSR as well as reading it, and the ability to load register lists from XML files to the built-in GDB server.

More details can be found on the QEMU wiki.

GCC 9.1 Adds New Backend for OpenRISC Support

The GNU Compiler Collection (GCC) 9 Release Series is now live, and GCC 9.1 brings with it the first support for the OpenRISC free and open source instruction set architecture.

“A new back end targeting OpenRISC processors has been contributed to GCC,” the release notes for GCC 9.1 explain — adding support for the instruction set architecture for the first time.

The port, which has Stafford Horne as its maintainer, was accepted by the GCC Steering Committee back in August 2018, and was accepted by a global reviewer for inclusion in GCC 9 shortly thereafter.

The backend has been integrated into GCC along with a range of other enhancements, improvements, and new features — but bracketed by the removal of support for the Solaris 10 operating system and Cell Broadband Engine SPU architecture.

Full details on the changes in GCC 9 can be found on the official website.

Michael Welling, Adam Vadala-Roth Announce Akita Project

Michael Welling and Adam Vadala-Rothhave announced a joint project dubbed Akita, as an entry into the Hackaday Prize 2019 and designed to combine embedded Linux and open source FPGA on a single board.

“It is a single board solution that combines an Octavo Systems SiP and the Lattice Semi ECP5,” Michael explains in the announcement on Twitter. “Think BeagleWire with a bigger FPGA all on a single board. We are calling it Akita.”

“Akita is being designed as a reference point for future projects based on the combination of the Octavo Systems Beagle SiP and Lattice ECP5 FPGA with 84K logic cells,” the pair explain in the project’s documentation. “The intention is that the schematic of Akita will serve as the starting point of a string of future projects and is being made open source so that others can have it as a starting point for their applications.”

The progress of the project can be tracked over on Hackaday.

VextRiscv/LiteX SoC Runs Upstream Kernel, Still FOSS Toolchain Compatible

David Shah has announced contributions from Papon Charles and Enjoy Digital which have allowed the VexRiscv/LiteX free and open source system-on-chip to run an upstream Linux kernel — while still maintaining the ability to be built using a free and open source toolchain.

“Thanks to the awesome improvements by @dolu1990 and @enjoy_digital,” David writes via Twitter, “the VexRiscv/LiteX 32-bit SoC can now run an upstream kernel! And it can all still be built with the FOSS FPGA tools and run on the ECP5 Versa board!”

Details of the changes required to add the support can be found in the now-closed pull request on the Enjoy Digital GitHub repository.

PULP Platform Updates RI5CY, PULPissimo Projects

The Parallel Ultra-Low Power (PULP) Platform has announced updates to its small four-stage RI5CY RISC-V core and RI5CY-based PULPissimo microcontroller architecture projects.

“As an Easter present,” the PULP Project announced via Twitter, “there is a new RI5CY update. It is now compliant to RISC-V Debug Spec v0.13. PULPissimo has also been updated and it should all work now with RISC-V OpenOCD.”

The latest release of the RI5CY core is available on the PULP Platform GitHub repository, alongside the PULPissimo project.