WOSH and the Google Summer of Code Kick Off
It’s finally here: the Week of Open Source Hardware starts today with two days of RISC-V workshops followed by two days of presentations and tutorials all around free and open source silicon topics. For those not attending, you’ll be able to read more about the event in next month’s El Correo Libre!
In other great news, the FOSSi Foundation has been accepted into the Google Summer of Code (GSOC) programme. In GSOC Google pays selected students a stipend for three months to work on open source projects. To ease the process for the rather small projects in the FOSSi ecosystem we are participating as an “umbrella” organisation and thereby allow projects to get a student to work with them for the summer. The goal is to involve new long-term contributors and improve the projects.
We have seven student projects this year:
- Analysis of WARP-V on FireSim with RocketChip, Alaa Salman
- Continuous Integration for Hardware Projects on LibreCores CI, Nancy Chauhan
- Enhancing JuxtaPiton with X86 Support, Kunal Gulati
- FPGA-Accelerated Web Applications, Ákos Hadnagy
- LLVM Code Generation for RISC-V Open Source GPU, Reshabh Sharma
- Microarchitectural enhancement of Ariane, Zach Zheng
All are fascinating project proposals, with coding now beginning, and we are looking forward to seeing great outcomes from the Summer of Code.
You can find more details in our blog post and can expect further status updates throughout summer!
-Stefan Wallentowitz, Director, Free and Open Source Silicon (FOSSi) Foundation
Rick O’Connor Announces the OpenHW Group, CORE-V Cores
Rick O’Connor, formerly the executive director of the RISC-V Foundation, has announced his next venture: the launch of a new not-for-profit global organisation dubbed OpenHW and the release of the CORE-V family of open-source RISC-V cores targeting system-on-chip (SoC) implementations.
“OpenHW Group is an organisation for collaborating with like-minded engineers,” Rick explains of the group’s aims. “If you’re an SoC designer, you don’t have to design from scratch; we will help you accelerate your design process by supplying you with a growing range of proven processor IP options, all available within an expanding, high-quality ecosystem. For example, for RISC-V-based processors, we’re introducing the CORE-V family of cores, which supports system-on-chip (SoC) hardware and software designers with a quality and manufacturability assurance when adopting RISC-V processor core IP.”
“The electronics industry is embracing open-source processor technologies at an unprecedented rate,” adds board chair Rob Oshana, vice president of software engineering at NXP Semiconductor. “At NXP we believe there’s a need to create a deep ecosystem to support adoption of the RISC-V ISA. This includes various components — middleware, stacks and tools — all aligned to move the architecture forward. I’m pleased to serve as Chairman of the OpenHW Group board to help realise this goal.”
The group has already attracted 13 sponsor organisations — including Alibaba, Bluespec, Embecosm, ETH Zurich, Greenwaves, Imperas, NXP, Silicon Labs, and Thales — and expects that figure to grow to 25 by the end of the year. The OpenHW Group is also a member of the RISC-V Foundation and has partnered, Rick explains, with the Eclipse Foundation.
“The FOSSi Foundation welcomes the OpenHW Group to the Free and Open Source Silicon ecosystem,” says Foundation director Philipp Wagner. “Their sustained development the CORE-V Family of open-source RISC-V cores will be of great benefit to the community. We applaud their efforts to explore an open and meritocracy-based contribution model for free/open silicon, enabling individuals to work as equals together with companies for the good of the whole ecosystem.”
More information is available on the official website.
Shah, Hung, Wilf, Bazanski, Gisselquist, Milanović Publish Yosys+nextpnr Paper
David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, and Miodrag Milanović have published a short paper on Yosys+nextpnr as part of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).
Properly titled “Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs,” the four-page paper acts as an introduction to using Yosys for Verilog synthesis and nextpnr for placement, routing, and bitstream generation.
“Currently, this flow supports two commercially available FPGA families,” the paper explains, “Lattice iCE40 (up to 8K logic elements) and Lattice ECP5 (up to 85K elements), and has been hardware-proven for custom-computing machines including a low-power neural-network accelerator and an OpenRISC system-on-chip capable of booting Linux.
“Both Yosys and nextpnr have been engineered in a highly flexible manner to support many of the features present in modern FPGAs by separating architecture-specific details from the common mapping algorithms. This framework is demonstrated on a longest-path case study to find an atypical single source-sink path occupying up to 45% of all on-chip wiring.”
The paper is available now on arXiv.org.
Dan Gisselquist Details “Perfect” AXI4 Slave, Releases AXI to AXI-Lite Bridge
Gisselquist Technology’s Dan Gisselquist has announced work on open Advanced Extensible Interface (AXI) implementations, detailing work on building “the perfect AXI4 slave” and the release of an AXI to AXI-Lite bridge which can sustain 100% throughput.
“Writing an AXI slave can be one of the more difficult challenges of FPGA design,” Dan explains by way of introduction to his blog post on the topic. “Don’t you just wish you could write a simple slave, and leave all that ugly AXI protocol stuff to a translator core?
“I had four primary goals in this exercise. The first was that my new AXI slave core needed to be AXI compliant. Realistically, that should be a given. However, we’ve already discussed how even Xilinx’s example code wasn’t truly AXI compliant, so I needed something new. My next goal was that this new core had to have maximum throughput. This second goal was so important to me that my third and fourth goals were identical: I wanted throughput! High throughput!”
Full details on the AXI4 slave design can be found on Dan’s blog post, while a tool for converting from AXI to AXI-Lite and capable of sustained throughput is available on the ZipCPU GitHub repository.
Matrix Releases Creator FPGA Source, Including Microphone DSP Code
Electronics company Matrix has announced the release of the full source code for the field-programmable gate array on its Matrix Creator board — including the digital signal processing (DSP) algorithms which drive its microphone.
“After much deliberation, we are happy to announce that we have decided to open up all of the FPGA source code, including the microphone digital signal processing algorithms, to our community,” explains community manager Samreen Islam. “We are now a 100% open-source software platform!
“We believe that this crucial step will further enable you to leverage the full potential of the Matrix platform by presenting you with the opportunity to modify and enhance the DSP for your project or product. As we continue to develop the Matrix platform, we are constantly looking for how we can improve, and best serve our community. We appreciate your continued support and we look forward to seeing what you create. Happy building!”
The Verilog code is available on the Matrix GitHub repository now, under the GNU General Public Licence 3.
lowRISC Unveils Google Partnership, Expansion Plans
The lowRISC project has announced a partnership with Google which will see the organisation expand its engineering team “significantly” before the year is out.
“Google has encouraged and supported lowRISC since the very start,” explains Alex Bradbury, co-founder and director of the lowRISC community interest company (CIC). “They clearly share our optimism for what open source hardware can offer and our community-driven vision of the future.
“We are excited by the expanding open source RISC-V ecosystem and look forward to lowRISC community IP being deployed in the real world. We believe lowRISC can act as an important catalyst for open source silicon, providing a shared engineering resource to ensure quality, provide support and help to maintain IP from a range of partners.”
“Google believes that open source is good for everyone,” adds Google’s vice-president of security Royal Hansen. “To further our commitment, we are investing both capital and engineering resources to create a sustainable open source hardware ecosystem. In addition to engineering resources, lowRISC provides the community stewardship that is vital to this vision.”
The partnership sees the appointment of two Google staff — Dominic Rizzo and Ron Minnich — to the lowRISC board, alongside new board member Professor Luca Benini of ETH Zurich.
More information, and a link to current job openings at lowRISC, can be found on the official website.
Antmicro Launches Renode 1.7 Branch
Antmicro has officially launched the 1.7 branch of Renode, the popular open-source simulation framework, bringing with it support for new soft-core implementations of the PicoRV32 and Murax SoC RISC-V based designs.
The new branch also includes experimental support for time-sensitive networking (TSN) and precision-time protocol (PTP), which were previously available exclusively as part of the Cadence GEM Ethernet controller. These features are part of Antmicro’s efforts to implement TSN and PTP in Zephyr for the Microchip SAM E70.
Other improvements available in the Renode 1.7 branch include improvements to the simulation’s execution determinism, better usability, and an integration layer for Verilator which allows Verilog implementations to be loaded into a Renode simulation.
More details are available on the Antmicro blog, while the latest release — 1.7.1 at the time of writing — can be found on the project’s GitHub repository.
Oğuz Meteer Adds Nexys Video Support to Linux on LiteX-VexRiscV
Programmer Oğuz Meteer has had a patch accepted to the Linux on LiteX-VexRiscv project — which, as the name implies, aims to experiment with Linux on a VexRiscv RISC-V-based system-on-chip built with LiteX — to add support for the Digilent Nexys Video board.
In a pull request accepted to the LiteX project last month, Oğuz’ contribution adds the first support for the Nexys Video board — building on the existing support for the Nexys 4 DDR, but offering users the ability to take advantage of four times the memory at 512MB as well as double the flash at 32MB and gigabit Ethernet support.
Work continues, meanwhile, to add support for the Radiona ULX3S board, progress on which can be followed in the project’s GitHub issue.
Details on Oğuz’ contribution can be found in the pull request, while the latest version of Linux on LiteX-VexRiscv is available from the official GitHub repository.
Clifford Wolf Releases v0.90 of the RISC-V Bit-Manipulation Extension Proposal
Clifford Wolf has officially published revision 0.90 of the RISC-V bit-manipulation extension proposal,” offering a firm look at the proposed bit-based instruction set extensions.
Designed, the BitManip Task Group explains, to “enable the development of code that is substantially more performant and efficient that what is possible with the base instructions,” the new instructions include operations which both improve performance and lower power requirements — though, as a trade-off, increase the complexity of the instruction set.
Originally published in 2017, the draft proposal has now reached a maturity level worthy of a jump from revision 0.36 to 0.90 — and with it a renaming of the project from XBitmanip to RISC-V Bitmanip. The specification, however, is still described as a work-in-progress, and while mature may not be adopted officially by the RISC-V Foundation in its current form without modifications that could render early implementations incompatible with any official release.
The latest version of the specification, along with reference implementations, formal proofs, models, and a reference simulation, can be found on the project’s GitHub repository.
European Processor Initiative (EPI) Announces “First Steps” Towards RISC-V Parts
The European Processor Initiative (EPI) has published a summary of its work six months after its founding, announcing the delivery of the first architectural designs to the European Commission.
“European Processor Initiative will deliver key technologies to the new European HPC [High-Performance Computing] strategic plan for an independent and innovative European high-performance computing and data ecosystem,” claims EPI board chair Marc Denis.
“Energy efficient high-performance families of EPI processors will include most advanced general-purpose and accelerator cores that will deliver unprecedented processing capabilities, enabling EU researchers from academia and industry to most efficiently address global challenges. The business sustainability of the initiative is supported by carefully balanced target markets, with primary focus on exascale HPC/AI and automotive markets.”
“Acceleration is crucial to continued performance gains while reducing power consumption in computing,” adds Professor Mateo Valero, director of the Barcelona Supercomputing Centre, of the organisation’s RISC-V projects. “In EPI, the first accelerator will begin from RISC-V technology to deliver two unique vector and artificial intelligence accelerators for HPC and AI, since future supercomputers will be mostly heterogeneous; the second accelerator, based on Kalray’s IP, will lead the path to deterministic automotive computation. Both are offering a European solution to future global converged (HPC and AI) computing needs.”
More details on the project can be found on the official website.
Libre RISC-V M-Class Project Announces NLnet Grant Funding
The Libre RISC-V M-Class project to create a fully-open RISC-V-based graphics processor has received €50,000 in funding from the NLnet Foundation and the European Commission’s Next Generation Internet initiative.
“The application for funding from NLnet and the Next Generation Internet initiative from the European Commission, from back in November of last year, has been approved,” explains project lead Luke Leighton. “It means that we have €50,000 to pay for full-time engineering work to be carried out over the next year, and to pay for bounty-style tasks. For the right people, with the right skills, there is money now available.
“More plans from our community are in the pipeline. We can apply for additional grants (also up to €50,000). In the next couple of days, we will put in an application for ‘Formal Mathematical Proofs’ of the processor design.”
More information on the funding and the status of the project as a whole can be found on its Crowd Supply campaign page.
FOSSi News In Brief
- David Shah: Blinkenlights on the Trellis Board Rev 1.0.
- iCEBreaker FPGA Early-Bird Shipping Complete.
- Imperas: “First RISC-V Simulator for New Vector and Bit Manipulation Specifications”.
- Codasip via Design & Reuse: “Extending RISC-V ISA with a Custom Instruction Set Extension”.
- Alex Bradbury via InfoQ: “The Future of Operating Systems on RISC-V”.
- Tõnis Tiigi: “Early look at Docker containers on RISC-V”.
- Wave Computing adds MIPS32 microAptiv Cores to MIPS Open Programme.
- EE Times: “EmBench Embedded Benchmark Calls for Support”.
- Imperas, Metrics Partner on Cloud-Powered RISC-V Core Design Verification.
- lowRISC: “An Update on Ibex, Our Microcontroller-Class CPU Core”.
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