ORCONF 2019 Three-Month Countdown Begins
It’s that time of year again. Following on from the FOSSi Foundation’s Latch-Up and WOSH events, ORConf is now less than three months away and if you haven’t heard, we’re hosting it in beautiful Bordeaux, France over the weekend of September 27th to the 29th.
ORConf is now in its eight year of bringing the open source silicon community together for a weekend of presentations, ideas, and discussions. We hope many of our fine past attendees will make the trip to France to join us again for what should be another fantastic event.
If you plan on coming along then please register here.
If you are joining us in a professional capacity, please consider purchasing a professional ticket here.
Presentation submissions are now open. We welcome everyone to come and tell us about your project, endeavour or your open source silicon use story. Presentation submissions may be made here
The call for sponsors goes out again this year — ORConf isn’t free to run and we rely on the generous support of companies and individuals to help put the event on. At this stage all sponsorship opportunities are available — so if you’d like to help the FOSSi Foundation fund the event, and get a great bit of recognition for it, then please get in touch with us via the links on orconf.org.
So, save the date and join us in Bordeaux for what will be another fantastic year of presentations and time spent face to face with the rest of the open source silicon community.
-Julius Baxter, Director, Free and Open Source Silicon (FOSSi) Foundation
OpenPiton Project Announces Release 12
The OpenPiton Project has officially announced Release 12 of its research-centric open-source processor design, marking the first time its OpenPiton+Ariane combination has been capable of booting a mainstream Linux kernel.
“This release brings several improvements to bring feature parity to Ariane,” explains OpenPiton’s Jonathan Balkind in the launch announcement, “alongside a number of smaller bug fixes [and the following new features].
“Addition of Ariane FPU on FPGA: With the addition of the Ariane FPU by default, OpenPiton+Ariane is now Linux distribution capable; First-class simulation simulation support for Verilator: This enables fast, fully open-source simulation of all of our supported cores; Simulation of OpenPiton+Ariane with VCS; Ethernet support for Ariane on FPGA.”
OpenPiton announced its partnership with the Parallel Ultra Low Power (PULP) Platform back in December 2018, combining the OpenSPARC OpenPiton design with the RISC-V PULP Ariane design with OpenPiton Release 10 as a means to create “the ideal permissive open-source RISC-V system.”
More information is available on the OpenPiton blog, or in the project’s GitHub repository.
Aquib Baig Details LibreCores Notification System Effort
Aquib Baig, one of the students participating in this year’s Google Summer of Code (GSoC) under the Free and Open Source Silicon Foundation (FOSSi Foundation), has written a post detailing work to develop a notification system for the LibreCores website.
“The basic idea was to generate notifications from the events that a user is associated with and notify the user about that event,” Aquib explains. “A simple example can be when a user creates a project, we can notify him that his project was successfully added to LibreCores.
“I had decided beforehand that there would be two types of notifications: App/Web notifications that appear on the user navbar and Email notifications that are sent directly to the email-id associated with the user. So, on the users perspective, his actions would generate these notifications.”
Aquib walks through problems encountered during the feature’s development — “they say you can plan any day but there will always be problems in the actual implementation,” he writes — and mentor and FOSSi Foundation director Philipp Wagner pointed him towards the RabbitMQ message broker platform to resolve them.
“It was a wonderful experience of learning and coding,” Aquib concludes. “After the first evaluations, we have to prepare for second round of coding and my goal [is the] introduction of User Feedback mechanism for LibreCores.”
More information is available on Aquib’s blog.
RISC-V Workshop Zurich 2019 Proceedings Published
The RISC-V Foundation has published official proceedings for the RISC-V Workshop Zurich, which took place between the 11th and 13th of June 2019 as part of the wider Week of Open Source Hardware (WOSH).
“The RISC-V Workshop Zurich showcased the open, expansive and international RISC-V ecosystem,” the organisation writes, “highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA), with a focus on the momentum and growth of the RISC-V ecosystem across Europe and beyond.”
“Over the last year or so, we’ve heard many times that ‘this is the moment for RISC-V.’ adds Embedded’s Nitin Dahad in a retrospective piece. “I attended the RISC-V workshop in Zurich to get an idea of where it really is at right now. The conclusion: while there is still a lot of background work to be done for RISC-V to go mainstream, the signs are that all the triggers to make it happen are now gradually being released.”
The full proceedings are available on the RISC-V Foundation website, and include slides for all presentations and video for most.
CERN Open Hardware Licence Team Seek Input on OHL Version 2
The team working on the second version of the CERN Open Hardware Licence — Myriam Ayass, Andrew Katz and Javier Serrano — have published a draft on which they are requesting feedback.
“Our current choice is to split the licence in three,” explains Javier. “A strongly reciprocal licence called CERN-OHL-S; a weakly reciprocal licence called CERN-OHL-L; a permissive licence called CERN-OHL-P.
“There was a demand for a permissive option in CERN OHL, and including it as an exception in the main licence text proved a bit cumbersome. Once we decided to split P, it also made sense to split L and S.”
The result is five documents total — one draft for each of the three licences, a frequently asked questions (FAQ) document, and a rationale — alongside an introductory video from Andrew Katz’ presentation at FOSDEM 2019. “If you would like to help us, it would be great if you found time to go through all this material,” Javier writes. “You can then send your feedback to us, either using the forum or writing to us directly.”
Links to all the documents, the video, and the forum for providing feedback are available from the Open Hardware Repository website.
IIT Madras’ Shakti Project Releases Public Software Development Kit
The Shakti Project, an effort by IIT Madras to build a family of RISC-V based processors ranging from embedded to high-performance compute parts for production within India’s borders, has hit a milestone following the booting of Linux on its first natively-built chip: the public release of the Shakti Software Development Kit (SDK).
Following funding from India’s Ministry of Electronics and Information Technology, Arvind Kumar, Sunita Verma, Tara Shanker, and Sandip Chatterjee created and released the official Shakti SDK under the GNU General Public Licence Version 3.
The SDK comes with instructions on downloading and setting the SDK up on an Ubuntu 16.04 host and walks through the SDK’s elements: projects, benchmarks, and examples; a board support package; documentation; ready-to-use tools, and a script for GDB debugging.
The SDK is available now on GitLab.
100 Days of FPGA and Digital Design with The Embedded Kitchen
Kumar Abhishek of The Embedded Kitchen has set himself a challenge: 100 days of FPGA and digital design, blogged daily on a new sub-site, as a means of challenging himself to learn new skills.
“As the name suggests, this sub-site of The Embedded Kitchen, is a 100-day challenge or solo boot camp for myself to ramp up on FPGAs and Digital Design,” writes Kumar. “I will be maintaining a record of what I do daily, how I learn in the interest of keeping track of my own progress as well as with the hope that it may help someone who is along a similar path.
“Something I have passed along the way but never took up and what prevents me from calling myself a ‘full-stack hardware engineer’ is FPGAs and digital design. Why did I pass it along for so long? Maybe because someone told me along the way that ‘FPGAs are only useful in huge industrial settings and there’s no point in learning it as a hobby.’
“Maybe because FPGAs looked cool from a distance but the toolchain and effort required to ramp up on them took long and scared me off? Maybe because they were priced way out of my budget and looked scary in an SMD or BGA package. Maybe because writing Verilog (or any other HDL) full time looked ‘less cool’ to me than the idea of designing boards and working with ‘physical hardware’.”
Deciding that none of these were deal-breakers, Kumar set himself the 100-day challenge which can be followed on its dedicated sub-site.
Philipp Wagner Publishes Update on lowRISC Ibex Core
FOSSi Foundation director Philipp Wagner has published an update on Ibex, a microcontroller-class CPU core designed as part of the lowRISC project.
“At the beginning of many chips projects, there’s a dream,” Philipp explains. “Could we create a more future-proof chip by embedding an FPGA fabric into it? Could we measure glucose levels more accurately by integrating a small bio lab onto a chip? Could we more reliably recognise kittens in a set of pictures by implementing neural network inference in hardware?
“In implementation, this dream becomes a piece of hardware, with digital or analogue logic, sensors, actuators, and much more. Let’s get it produced and try out the real thing! But wait. How do you control the hardware block? How do you feed data to it? How do you make sure the startup sequence is done exactly in the right way? The answer often is: add an embedded micro-controller core to handle the control logic. A small, efficient, and rock-solid core. Where could you get such a core?
“Say hello to Ibex: a small, 32-bit microcontroller-class RISC-V CPU core written in SystemVerilog. Reliable, unpretentious, getting the job done.”
Full details on Ibex, which is made available under the permissive Apache 2.0 licence, can be found on the lowRISC blog.
Trammell Hudson Releases SPI Spy Flash Emulation Utility
Trammell Hudson has officially released SPI Spy, an open-source utility designed to emulate Serial Peripheral Interface (SPI) flash using a Lattice ECP5–12F FPGA on the Radiona ULX3S development board.
“The SPI Spy is an open source (both hardware and software) SPI flash emulation tool. It can store a flash image in the SDRAM connected to the FPGA and serve the image to a host CPU over the SPI bus,” Trammell writes. “This allows you to avoid the lengthy SPI flash erase/write cycles during firmware development as well as to more easily explore early boot time security against TOCTOU attacks.
“The design is currently based on the ULX3S which has an Lattice ECP5–12F FPGA and a 16-bit wide 32 MB SDRAM. It might be portable to the TinyFPGA-EX or other open source ECP5 boards, although it uses a custom SDRAM controller to be able to meet the difficult timing requirements of the SPI flash protocol.”
The first release was only the beginning of the project, too: recently Trammel added support for the Read SFDP (0x5A) command, “which allows it to boot more modern mainboard chipsets like the SuperMicro X11SSH and the ASRock H110M.”
SPI Spy is available now on the OS Research GitHub repository.
Antmicro Releases Cocotb, Verilator Integration for Speedier FPGA Testbenches
Antmicro has published a blog post detailing its work with FOSSi Foundation director Stefan Wallentowitz and Western Digital to integrate Cocotb — the Coroutine-based Cosimulation Testbench — and Verilator, promising it will “speed-up your FPGA testbench development.”
“Related to our joining of the CHIPS Alliance, an organisation which aims to push for verified end-to-end open source silicon designs based on open tooling, together with our fellow CHIPS Alliance and RISC-V Foundation member Western Digital we were looking at how to foster collaboration across different but neighbouring communities,” Antmicro writes, “and integrating Cocotb with Verilator seemed like an ideal pick.
“Based on the earlier work of and in collaboration with FOSSi Foundation’s fellow director, Stefan Wallentowitz, and through the kind sponsorship of Western Digital, we implemented a robust and tested Cocotb and Verilator integration — pending upstreaming. Cocotb will now be able to generate a generic C++ testbench of the verilated design, build and run it, using VPI to control the simulation process.”
While the work has not yet been upstreamed, instructions on using Antmicro’s integrated build can be found on the company’s blog post.
OpenROAD Opens Nominations for Open-Source Community Contribution Awards
The University of California at San Diego’s OpenROAD Project, founded in an attempt to find ways to reduce the barriers to entry in hardware design through open source methodologies, has opened nominations for its Open-Source Community Contribution Awards (OSCCAs).
“The OpenROAD project is pleased to announce the establishment of its Open-Source Community Contribution Awards,” the organisation writes. “New open-source contributions in the realm of physical implementation and validation for IC, package or board design can be nominated for an Award. Awards in the range of US $250 to US $2000 will be made periodically by an industry review panel led by Dr. Paul Penzes (VP Engineering, Qualcomm).”
Anyone is able to submit nominations, including self-nominations, but the awards are not available to anyone who has received funding from OpenROAD in the last 12 months. Priority will be given, the organisation claims, to projects which are made available under permissive licences like BSD, MIT, and Apache, as well as those which function within existing workflows.
More information, and a link to make a nomination, is available on the OpenROAD website.
FOSSi News In Brief
- AB Open: “Digital FOSSils: A History of Free and Open-Source Silicon.”
- Hackaday: “FPGA Soft CPU is Superscalar.”
- University of Berkeley: “New RIOS [RISC-V International Open Source Laboratory] to Expand Open-Source Ecosystem.”
- Greenwaves: “GAPPoc: A Family of GAP-Centric Proof of Concept Boards for Edge AI.”
- X-FAB, Efabless Announce Raven Mixed-Signal RISC-V System-on-Chip Design.
- Kickstarter: “WebFPGA Rapid FPGA Development Platform.”
- IEEE Spectrum: “DARPA’s $1.5-Billion Remake of US Electronics: Progress Report.”
- Western Digital Partners with SiFive, PlatformIO Labs to Extend PlatformIO Toolset.
- Western Digital: “OmniXtend Cache-Coherent Fabric Drives Innovation with RISC-V.”
- DataCenter Knowledge: “SiFive CEO Says RISC-V Servers are ‘Five Years Away.’”
- Manuel Montecelo: “Debian GNU/Linux riscv64 Port in Mid 2019 [Progress Report].”
- InAccel Releases Open-Source Logistic Regression IP Core for FPGAs.
- Embench Team Calls for Assistance to Develop a Fully-Open Embedded Benchmark.
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