Gareth Halfacree
Aug 13 · 11 min read

LibreCores Refreshed while ORConf 2019 Speakers Confirmed

Free and open source is all about sharing and reuse. Sharing ideas, sharing algorithms, and most importantly, sharing code. Sharing code requires two things: someone who publishes it, and someone who uses it — along with a connection between the two. This connection is provided by LibreCores, the project repository site maintained by the FOSSi Foundation. LibreCores enables developers to showcase their digital hardware projects, and it makes them discoverable for others to reuse and build on.

LibreCores has been up and running for a couple years now, and this summer it got even better. Thanks to the great work by Amitosh Swain we have fixed many issues to make it easier than ever to add new projects to the site, and to reliably retrieve contents from the project’s source repository. Thanks to the new notification system designed and developed by Aquib Baig, this year’s Google Summer of Code Student, we can now communicate more effectively with our users.

To make LibreCores even better, we need you: do you maintain a project which isn’t yet on LibreCores? Add it now — it’s free to do so, of course! We also invite you to spread the word about LibreCores, and please do let us know if something doesn’t work as expected by filing an issue on GitHub.

We are also pleased to announce that the first batch of speakers for ORConf, the open-source digital design conference organised by the FOSSi Foundation, has been confirmed. Full details of the event, which takes place on the 27th to 29th of September 2019 in Bordeaux, France, can be found on the official website. As always, we’d love to see you there!

-Philipp Wagner, Director, Free and Open Source Silicon (FOSSi) Foundation

RISC-V Foundation Ratifies Base, Privileged Specifications

The RISC-V Foundation has officially ratified both the base RISC-V instruction set architecture (ISA) and privileged architecture specifications, guaranteeing that designs made to the current version of the standard will be fully compatible with future releases.

“RISC-V was designed with a simple fixed base ISA and modular fixed standard extensions to help prevent fragmentation while also supporting customisation,” says Krste Asanović, chair of the RISC-V Foundation board. “The RISC-V ecosystem has already demonstrated a large degree of interoperability among various implementations.

“Now that the base architecture has been ratified, developers can be assured that their software written for RISC-V will run on all similar RISC-V cores forever.”

The ratification covers both the base ISA and the privileged architecture specifications. “The RISC-V privileged architecture serves as a contract between RISC-V hardware and software such as Linux and FreeBSD. Ratifying these standards is a milestone for RISC-V,” adds Andrew Waterman, chair of the RISC-V Privileged Architecture Task Group. “Operating system developers and hardware vendors can build to these specs with confidence that their work will be compatible.”

Both specifications are available now from the RISC-V Foundation website.

CHIPS Alliance, Western Digital, Olof Kindgren Launch SweRVolf SoC

FOSSi Foundation director Olof Kindgren, in partnership with the CHIPS Alliance and Western Digital’s director of next-generation platforms technology Zvonimir Bandic and outgoing chief technology officer Martin Fink, has released a new system-on-chip design based on the open SweRV RISC-V core.

T”he idea is to offer a portable and extendable SoC for FPGA and simulation to experiment with the SweRV EH1 core,” Kindgren explains. “[It] initially targets the Digilent Nexys A7 FPGA board and simulations with Modelsim or Verilator. Using FuseSoC this can quickly be ported to other targets too.

“This is also a testament to the vibrant FOSSi ecosystem as it combines IP cores and tools from many different developers and groups around the world to create a fully open source project that can be used in industry, academia or by curious hobbyists.

“To give some examples, apart from Western Digital’s CPU most AXI infrastructure comes from PULP Platform, DDR2 controller from Enjoy Digital, OpenOCD integration by M Labs, and others. Debug IF leans on lowRISC work, my very own FuseSoC and many more.”

SweRVolf is available now from the CHIPS Alliance GitHub repository.

Berkeley HardFloat Gets First Verilog Release

Berkeley HardFloat, the hardware floating-point modules designed by the University of California at Berkeley, has hit Release 1 status with the release of its Verilog files.

“Berkeley HardFloat is a free, high-quality Verilog encoding of digital hardware modules for binary floating-point arithmetic,” explains creator John Hauser of the project. “HardFloat fully conforms to the IEEE Standard for Floating-Point Arithmetic, supporting all required rounding modes, exception flags, and special values, including subnormals.

“HardFloat is written for the 2001 standard for Verilog. Different floating-point specialisations are provided to customize the arithmetic appropriately for Intel x86, Arm, or RISC-V processors. Other specialisations can be crafted using these as examples.”

More information on using and testing Berkeley HardFloat can be found on Hauser’s website.

Yosys Seeks Feedback on 0.9 Release Candidate Branch

Yosys, the popular framework for Verilog synthesis, is heading into its 0.9 release — and a release candidate branch is available now for those willing to try it out and provide feedback.

“There’s now a Yosys-0.9 release candidate branch,” writes Clifford Wolf via Twitter. “Please give it a thorough test and report any issues you might find. (If you report issues on GitHub make sure to mention that they are for the RC branch.)”

“I’m really excited about some synthesis improvement work I am doing in the recent days in Yosys. I think major improvements in synthesis quality are possible & close,” adds developer Whitequark of some improvements coming to future releases. “By ‘synthesis quality’ I mean both the improvements in delay/area (which is what everyone aims for), and the improvements in debug information (which is a secondary goal at best for most EDA tools).

“I am also aiming to improve synthesis such that you get the ‘butterfly effect’ less often; that effect being when you change one part of the design and it totally perturbs the synthesiser output in hard to understand and often undesirable ways. I am very, very tired of trying to optimise my CPU only to see that clear simplifications in logic (for example, taking a single assignment out of an FSM and making it a direct connection between submodules) can result in increase in LUT count by as much as 20% of the total.”

The Yosys 0.9 Release Candidate branch is available now on the project’s GitHub repository.

Pepijn de Vos Demonstrates VHDL-to-PCB Workflow for 74-Series Logic Project

Engineer Pepijn de Vos has demonstrated a workflow which has produced a functional circuit board for a 74-series TTL logic board directly from VHDL, without the need to design the board by hand.

“I had been keeping an eye on Yosys, the open source HDL synthesis tool, which can apparently do ASIC by giving it a liberty file that specifies the logic cells your foundry supports,” de Vos explains. “Meanwhile I also toyed with the idea of making a 7400 series computer, and I wondered if you could write a liberty file for 7400 chips. I had kind of dismissed the idea, but then ZirconiumX [Dan Ravensloft] came along and did it.

“Generating a Yosys netlist is nice, but eventually these 7400 chips have to end up on a PCB somehow. Normally you draw your schematic in Eeschema, generate a netlist, and import that to Pcbnew. But instead I used skidl to generate the netlist directly. Then all there is to do is add the inputs and outputs and run the autorouter (or do it manually of course).

“This was all done in Verilog, so where is the VHDL, you might wonder. Well, Yosys does not really support VHDL yet, but Tristan Gingold is hard at work making GHDL synthesise VHDL as a Yosys plugin. I think this is very important work, so I’ve been contributing there as well. After some pull requests I was able to port the breathing LED to VHDL.”

A video demonstration of the board is available on YouTube, while the full project write-up can be found on de Vos’ blog.

Colin Riley’s CPU-Designing Series Continues

Domipheus Labs’ Colin Riley is continuing to update his multi-part write-up on designing a RISC-V processor in VHDL, which has recently reached its 18th entry — the design of the control and status register unit.

“Why design my own CPU, with associated ISA, assembler and other tools? Because, I can! Why not? I’ll learn a load of stuff,” Riley wrote of his original inspiration for the series. “As a software developer, and in particular, a compiler/debugger engineer, you are exposed to low level architectural details, latencies, hazards and of course, hardware bugs.

“In the past I’ve been part of teams who have been able to feedback details of architectural quirks that, if modified, can improve throughput in certain workloads — sometimes, completely new features have been added to hardware due to feedback. However, as a software engineer, you are limited in exposure to what that actually boils down to at the hardware level. It’s an area of computer science which fascinates me and I’d very like to get more involved in.”

Riley’s original plan was to create a CPU based on a 16-bit instruction set architecture he had designed; in Part 15 of the series this was changed to the RV32I RISC-V ISA, development on which continues.

An index with links to each entry in the series, along with GitHub repositories containing the sources, can be found on the Domipheus Labs website.

Ben Eater Builds “The World’s Worst Video Card”

A pair of educational videos from Ben Eater demonstrate what he suggests may be the “world’s worst video card,” built on a breadboard using discrete logic chips.

“Let’s build a circuit that displays an image on a VGA monitor,” Eater writes by way of introducing the project. “In this video, I talk about how VGA signals work and build a circuit that provides the correct timing of sync signals so that a monitor recognises the signal.

“In part 2, I talk about how VGA uses analogue RGB signals to send different colour pixels to the monitor. I use an EEPROM to store an image and build a simple digital-to-analogue converter to generate the colour signals to successfully display an image.”

The functional device at the end serves as a high-quality introduction to what goes into building a video signal, though may not be replacing commercial graphics card IP in the near future.

Part 1 and Part 2 are available on Eater’s YouTube channel now.

Tom Verbeure on Building Multiport Memories with Block RAMs

Tom Verbeure has written an article on building multiport memories with block RAMs, covering various common methods and one novel method with fewer restrictions.

“On-chip memories are one of the key ingredients of digital design,” Verbeure writes. “In an ASIC design environment, you are typically offered a library of various configurations: single read/write port, single read/single write ports, sometimes dual read/write ports.

“In FPGA land, things are more limited: you get to use what the FPGA provides and that is that. In this blog post, I go over the some common ways in which multiple read and write port memories can be constructed out of standard BRAMs. I then describe a really interesting way in which they can be designed without any major restrictions other than the number of BRAMs in your FPGA.”

The full piece is available on Verbeure’s GitHub page.

David Shah Demos RISC-V Linux Boot using Open-Source Toolchain

Symbiotic EDA’s David Shah has demonstrated a successful boot into the Linux kernel on a RISC-V soft core running on a Lattice Semiconductor ECP5 FPGA, using an open-source toolchain to generate the bitstream.

“Our team member [David Shah] demoed how to boot Linux on a RISC-V core emulated on a [Lattice Semi] ECP5 FPGA,” Symbiotic EDA announced on its Twitter account. “The bitstream for the FPGA was generated with open source tools written by our team-members.”

“Bitstream for FPGA was generated with open source tools,” adds Edmud Humenberger, who uploaded the video to YouTube. “Yosys and nextpnr and project Trellis only. RISC-V core is [VexRiscv].”

The short video is available now on YouTube.

DARPA’s OpenROAD Alpha Release Now Available

The US Defence Advanced Projects Agency (DARPA)’s OpenROAD project — Foundations and Realisation of Open, Accessible Design — has announced its alpha release, offering a look at what the initiative has put together thus far in its attempts to create a fully autonomous open-source tool chain for digital layout generation.

“The IDEA programme targets no-human-in-loop (NHIL) design, with 24-hour turnaround time and eventual zero loss of power-performance-area (PPA) design quality,” the project summary explains. “No humans means that tools must adapt and self-tune, and never get stuck: thus, machine intelligence must replace today’s human intelligence within the layout generation process.

“24 hours means that problems must be aggressively decomposed into bite-sized sub-problems for the design process to remain within the schedule constraint. Eventual zero loss of PPA quality requires parallel and distributed search to recoup the solution quality lost by problem decomposition.”

The alpha release is available on the OpenROAD GitHub repository now.

FOSSi News In Brief

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News and features from the world of free and open source IP cores

Gareth Halfacree

Written by

Freelance journo. News editor, Author, Raspberry Pi & BBC Micro:bit User Guides. Custom PC columnist. Bylines in PC Pro, The MagPi, HackSpace etc.


News and features from the world of free and open source IP cores

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