El Correo Libre Issue 19

Published in

LibreCores

16 min readSep 10, 2019

Google Summer of Code Students Complete Their Welcomed Contributions

What an exciting summer! We at FOSSi Foundation are happy to announce that all of our Google Summer of Code (GSoC) students this year successfully completed their projects. For multiple years now, FOSSi Foundation has acted as umbrella organisation for multiple GSoC projects. All projects were mentored by trusted community members, and we’re extremely happy how well the projects went! We owe a big thank you to all students and mentors, thanks to you, the free and open source hardware ecosystem is in a better place than before.

Ákos Hadnagy returned to GSoC this summer, making significant contributions to the “1st CLaaS” framework for developing hardware-accelerated web applications and microservices (where CLaaS stands for Custom Logic as a Service). 1st CLaaS provides the communication channel for applications to stream bits to and from custom hardware logic via REST requests and WebSockets. It reduces integration overhead for Amazon F1 FPGAs from months to hours, thereby bringing this burgeoning new world within reach of hobbyists and the open-source community.

Ákos’s contributions are in the GitHub repo. Ákos summarised his work in a LinkedIn article. Ákos was mentored by Steve Hoover.

Alaa Salman’s contributions in GSoC 2019 centred around the WARP-V RISC-V core generator written in TL-Verilog. Alaa first explored the integration of WARP-V with RocketChip, a Chisel RISC-V SoC from UC Berkeley. The goal was to leverage the RocketChip SoC infrastructure and swap out the CPU core for various WARP-V cores. This would enable Linux boot and performance studies with different WARP-V configurations. Alaa completed a proof-of-concept exercise to path-clear the various technologies involved, he identified the boundary at which this “lobotomy” would be performed, he defined the necessary logic changes, and he refined the timeline based on discoveries. This exposed some schedule risk, so Alaa’s work was redirected to implementation characterisation and optimisation of WARP-V. Alaa generated insightful data showing area/clock-speed tradeoffs with different WARP-V configurations and tool settings, and he identified a key critical path that was addressed by a parameter change for a significant clock speed improvement.

Alaa’s contributions are in the GitHub repository. Alaa also summarised his work in a LinkedIn article. Alaa was mentored by Steve Hoover.

Aquib Baig worked on a notification system for LibreCores. He added the ability to inform its users about problems when analysing a project on LibreCores, about the need to update credentials, and much more. With this new notification system in place, we now have a feedback channel to our project owners, helping them to get the most of of LibreCores. Read more about Aquib’s work in his summarising blog post.

Aquib was mentored by Philipp Wagner with support from Amitosh Swain.

Kunal Gulati worked on integrating the ao486 processor into the OpenPiton many-core research framework. Recently, OpenPiton was extended as JuxtaPiton, which brought together cores of two different ISAs (SPARC + RISC-V) to explore how to build such a heterogeneous ISA system. Kunal’s project was to connect an X86 core to bring a new form of ISA heterogeneity. Over the summer, he wrote a new memory transducer from the core’s Avalon memory interface to OpenPiton’s P-Mesh memory system and an I/O transducer to handle several of the legacy peripherals (timers, clock, interrupt controller). He modified the BIOS distributed with the Bochs X86 emulator to remove unused peripherals and was able to run this BIOS on ao486 connected to P-Mesh. On top of the BIOS, he built assembly tests in a boot sector which can access the standard peripherals (UART, SD, etc) in OpenPiton using memory-mapped I/O. Kunal did an amazing job to get all this working and we both learned a lot of low-level X86 details along the way. Thanks Kunal!

Kunal’s Medium article explains his contributions more and links to the PRs that he made as part of the project. Kunal was mentored by Jonathan Balkind.

Nancy Chauhan worked on improving LibreCores CI by example: switching the continuous integration for the mor1kx OpenRISC CPU core to use LibreCores CI. Her work included improvements to multiple tools used across the build pipeline, from Docker and Jenkins to yosys and edalize. The CI now includes steps to run an Icarus Verilog simulation with different mor1kx configurations (e.g. with and without data caches), and a Yosys synthesis to report the resource usage of the core.

Nancy summarised her work in a FOSSi Foundation blog post. Nancy was mentored by Oleg Nenashev and Stafford Horne.

Reshabh Sharma worked on LLVM improvements for a RISC-V GPGPU. Recently, as part of the evolving BaseJump many-core open source RISC-V GP-GPU effort, U. Washington taped out an open source RISC-V many-core processor with 496 cores that hits 695 Billion RISC-V instructions per second using 12 mm2 of area. The silicon is up and running in the lab and broke several world records for both RISC-V instruction throughput and RISC-V energy efficiency. A second generation design is being developed based on results from the first generation, with a target of improving programmability. This GSoC project focused on extending the 32b RISC-V LLVM compiler implementation to allow a 32-bit RISC-V ISA to leverage 64-bit pointers for accessing a large pool of DRAM, but retaining 32-bit pointers for accessing local memory. Reshabh Sharma tackled this complex task handily, navigating the perilous waters of LLVM, leveraging the expertise of the LLVM community, and explored many options until he finally found a combined solution that was effective.

A pull request with summary as comment is available on GitHub. Reshabh summarised his findings in a blog post at the FOSSi Foundation blog. Reshabh was mentored by Michael Taylor.

Zach Zheng improved the microarchitecture of Ariane, an open-source 64 bit, application-class RISC-V core. In particular, his contributions included IPC improvements by employing a new global predictor and making the processor a super-scalar implementation. To sustain the higher instruction throughput Zach had to widen the instruction fetch interface to support 64 bit fetch packages. This included modification to the instruction re-aligner which handles 16 bit compressed instructions. In the next phase, Zach had to adapt the branch-prediction interface to handle the widened instruction fetch interface. In addition, he added a new global predictor (GSHARE). Final he added a second issue port to the execute stage as well as another arithmetic logic unit (ALU) to take full advantage of the dual-issue capabilities. In addition, he benchmarked his contributions, both in IPC increase as well as FPGA resource utilisation.

For a detailed explanation, you can visit his GSoC project page. Zach was mentored by Florian Zaruba.

-Philipp Wagner, Director, Free and Open Source Silicon (FOSSi) Foundation

Final Call for ORConf 2019

It’s September, which means ORConf 2019 is afoot. Now in its eighth year, the leading international event for the free and open source silicon community is being hosted this year in Bordeaux, France over the weekend of the 27th to 29th of the month.

The schedule is now available, detailing presentations from industry and community luminaries including the RISC-V Foundation’s Calista Redmond, the CHIPS Alliance’s Zvonimir Z. Bandic, the OpenHW Group’s Rick O’Conner, David Shah, Tim ‘mithro’ Ansell, Dan Gisselquist, Pepijn de Vos, Andrew Katz, Stafford Horne, and of course FOSSi Foundation members including Philipp Wagner and Julius Baxter.

Topics range from a general look at the free and open source silicon movement itself to specific cores and projects including CORE-V, RudoIV, SCR1, OpenRISC, and ASICone, tools including coctb, netlist-paths, GNU poke, TerosHDL, and nextpnr, a talk on the Embench benchmark suite, and more.

Free general and paid professional tickets — proceeds from the latter being used to fund the event, alongside sponsorship from Western Digital, the OpenHW Group, Antmicro, Hudson Trading, Embecosm, Hiventive, and the FOSSi Foundation itself — are still available, with full details found on the official website.

IEEE Standards Association Approves VHDL-2019 as IEEE 1076–2019

The Institute of Electrical and Electronics Engineers (IEEE) Standards Association Standards Board has officially approved IEEE Standard 1076–2019, better known as VHDL 2019, paving the way for its official public release.

The VHSIC Hardware Description Language (VHDL) was last formalised in an IEEE Standard in 2008, and published in 2009, as IEEE 1076–2008. Work on extending and improving the language led to a proposed update, VHDL-2017 — but delays meant that VHDL-2017 would become VHDL-2018, then VHDL-2019. Thankfully, those delays appear to be finally at an end, and VHDL-2019 will form the official release of the standard.

“IEEE Std 1076–2019 has been approved by the IEEE SASB today,” announced IEEE Standards Association manager Jonathan Goldberg on the organisation’s official mailing list. “Congratulations and thank you for your hard work!”

VHDL-2019 brings a range of improvements, many of which are detailed on VHDL Whiz, including automatic garbage collection to resolve memory leaks, new procedures and functions, support for 64-bit long integers, and conditional compilation.

The IEEE Standards Association has not yet publicly published the IEEE 1076–2019 standard, but is expected to do so in the coming weeks.

OpenPower Joins the Linux Foundation, Opens the Power ISA

The OpenPower Foundation has announced an alliance with the Linux Foundation to release the Power instruction set architecture (ISA) under a permissive licence, which has already resulted in the release of the first open Power softcore.

First released in 1992 as PowerPC by the Apple-IBM-Motorola partnership AIM, the Power architecture was promoted by the OpenPower Foundation — but, despite the name, was never made available under a free or open source licence, until now.

“By moving the Power ISA under an open model — guided by the OpenPower Foundation within the Linux Foundation — and making it available to the growing open technical commons, we’ll enable innovation in the open hardware and software space to grow at an accelerated pace,” claims OpenPower Foundation executive director Hugh Blemings. “The possibilities for what organisations and individuals will be able to develop on POWER through its mature ISA and software ecosystem will be nearly limitless.”

“The OpenPower community has been doing critical work to support the increasing demands of enterprises that are using big data for AI and machine learning workloads,” adds Linux Foundation executive director Jim Zemlin. “The move to bring these efforts together with the worldwide ecosystem of open source developers across projects at The Linux Foundation will unleash a new level of innovation by giving developers everywhere more access to the tools and technologies that will define the next generation of Power architecture.”

The Power ISA v3.0B is available to download now from the OpenPower Foundation website, while the first permissively licensed Power softcore, Microwatt, can be found on GitHub under a Creative Commons Attribution 4.0 licence.

MIT Engineers Build First Carbon Nanotube RISC-V Chip

Researchers at the Massachusetts Institute of Technology (MIT) have announced the world’s largest test chip built using carbon nanotube transistors (CNTs), a potential future replacement for silicon transistors in semiconductors, and it implements the open RISC-V ISA.

“This is by far the most advanced chip made from any emerging nanotechnology that is promising for high-performance and energy-efficient computing,” claims Professor Max M. Shulaker of his team’s work on the test chip. “There are limits to silicon. If we want to continue to have gains in computing, carbon nanotubes represent one of the most promising ways to overcome those limits. [This paper] completely re-invents how we build chips with carbon nanotubes.”

The team’s work is based on a novel technique dubbed Designing Resiliency Against Metallic CNTs (DREAM), which is claimed to dramatically reduce the number of defects occurring during CNT production — allowing the production of a 14,000-transistor chip in a field which was previously limited to triple-figure transistor counts.

Details on DREAM and the RV16XNano chip it produced, which posted a customised Hello World message to prove its functionality, can be found in the journal Nature.

SweRV EH1 Core Gets a FuseSoC-Based System on Chip: SweRVolf

The SweRV EH1 core released by Western DIgital now has a system-on-chip (SoC) implementation dubbed SweRVolf, released by the CHIPS Alliance based on a collaboration between FOSSi Foundation director Olof Kindgren, Western Digital Director of Next Gen Platforms Tech Zvonimir Bandic, and the company’s outgoing chief technology officer Martin Fink.

“The idea is to offer a portable and extendable SoC for FPGA and simulation to experiment with the SweRV EH1 core,” Olof explains. “Initially targets the Digilent Nexys A7 FPGA board and simulations with Modelsim or Verilator. Using FuseSoC this can quickly be ported to other targets too.

“This is also a testament to the vibrant FOSSi ecosystem as it combines IP cores and tools from many different developers and groups around the world to create a fully open source project that can be used in industry, academia or by curious hobbyists. To give some examples, apart from Western Digital’s CPU most AXI infrastructure comes from PULP Platform, DDR2 controller from Enjoy Digital, OpenOCD integration by M Labs, and others. Debug IF leans on lowRISC work, my very own FuseSoC and many more.”

The SoC is available now on the CHIPS Alliance GitHub repository. Martin Fink, meanwhile, has announced he is to retire as chief technology officer of Western Digital but will remain available in an advisory capacity for what the company describes as “matters relating to data centre architectures, including RISC-V.”

CAPS Research Group Launches MARSS-RISCV Cycle-Accurate System Simulator

The CAPS Research Group at Binghamton University (SUNY-Binghamton) has announced the launch of the Micro-Architectural System Simulator for RISC-V (MARSS-RISCV).

“MARSS-RISCV [is] a true full system, cycle-accurate simulator for RISC-V processors,” explains group member Parikshit Sanraik of the release. “MARSS-RISCV can simulate the execution of applications, OS (including system calls), libraries, interrupt handlers and boot loaders, cycle-by-cycle on pipelined implementations.”

“Some of the features of MARSS-RISCV include: True full system simulation — simulates in a cycle-accurate fashion the execution of instructions in the entire software stack including the boot-loader, system calls and OS code, libraries, interrupt handlers, user-level applications, etc; fully configurable, cycle-accurate, in-order and out-of-order single-core RISC-V CPU with support for RV32GC and RV64GC (user-level ISA version 2.2, privileged architecture version 1.10);

“Multiple execution units with configurable latencies (execution units can be configured to be pipelined); 2-level cache hierarchy with various allocation and miss handling policies; A simple DRAM model that accounts for open-page hits; A variety of branch predictors: bi-modal and 2-level adaptive (Gshare, Gselect, GAg, GAp, PAg, PAp); Supports VirtIO console, network, block device, input, and 9P filesystem.”

The simulator, currently in alpha and soliciting feedback, is available now on the CAPS GitHub repository.

Dan Gisselquist on Saving Logic While Adding Peripheral Devices

Dan Gisselquist has published a blog post detailing how to add lots of devices to a bus without using up a lot of logic in a design — increasing the number of peripherals that can be included in a given core.

“I’m not quite sure why, but most of the time when I examine a design on-line that someone has posted to a forum, there are very few bus components. There’s typically a CPU (Microblaze, Nios2, or ARM), some kind of SDRAM memory, perhaps a flash device, and then one or two other peripherals. Perhaps these would be an SD-card controller and an ethernet controller,” Dan writes. “I’ve never quite understood this. Many of my own designs will have those same peripherals, but then perhaps another 25 more. Why not create more peripherals than just a few?

“My guess is that it costs most folks too much logic. Perhaps this is why I’ve never seen more than a couple of slaves in any particular design: the interconnect alone might take nearly half the part, if not more! (Depending upon your FPGA size, of course.) This of course leads to the interesting question, how is it that I haven’t suffered from this problem when adding 20+ peripherals to a design?”

The answer to Dan’s puzzler can be found on the ZipCPU website in full detail.

Pepijn de Vos on Open-Source Formal Verification in VHDL

Engineer Pepijn de Vos has published a piece on his work with formal verification using VHDL and an open-source tool chain — which is also to form the topic of his talk at ORConf later this month.

“I believe in the importance of open source synthesis, and think it’s important that open source tools support both Verilog and VHDL,” Pepijn writes. “This week we reached what I think is an important milestone: I was able to synthesise my VHDL CPU and then formally verify the ALU of it using completely open source tools.”

Pepijn’s tool chain is based around Yosys, nextpnr, SymbiYosis, GHDL, and the ghdlsynth-beta plugin which allows GHDL’s synthesis format to be converted to the intermediate representation of Yosys — “the goal is to eventually upstream it into Yosys,” he explains of the tool.

“I think formal verification sounds harder and more scary than it is. An alternative description is property testing with a SAT solver. Think Quickcheck, not Coq. This is much simpler and less formal than using a proof assistant. Basically you describe properties about your code, and SymbiYosys compiles your code an properties to a netlist and from a netlist to Boolean logic. A SAT solver is then used to find inputs to your code that (dis)satisfy the properties you described. This does not “prove” that your code is correct, but it proves that it satisfies the properties you defined.”

Pepijn’s full post, including instructions for following along yourself, is available on his website; attendees to ORConf on the 27th to 29th of September will also be able to see him present on the topic.

Greg Davill Details OrangeCrab Board Bring-Up Process

Greg Davill has built and begun using the first OrangeCrab boards, Feather-format development boards based on the Lattice ECP5 field-programmable gate array (FPGA).

Greg details the process of manufacturing and bringing up the boards in an impressive Twitter thread which began back in July with a look at the KiCad project files. In early August the physical boards arrived, and assembly began. After painstaking work, the first board was finished — and bring-up began.

“First step of bring-up, apply power and check for valid voltages. All 4 power rails look okay,” Greg writes. “Battery charger is working. CHG status works. Green when the board is powered from external power; Yellow when charging; No colour when running just off battery.

“I’m a big fan of ‘Just in Time Learning”, picking up skills and new concepts as you need them. But I probably should have studied how DDR3 works before building a PCB using DDR3… I am making progress though!”

The full thread is available on Twitter, while more information on the OrangeCrab itself can be found on the project’s GitHub repository.

1BitSquared Publish iCEBreaker Production Progress Update

Piotr and Danika, of 1BitSquared, have announced that production and shipping of the iCEBreaker FPGA development boards continues — while highlighting a small issue with an accidental switch to a new LED.

“Production is going well and has been pretty smooth,” the pair explain in a campaign update. “We did run into one issue during assembly. Piotr used up a reel of green LED, after the reel was empty he started using a new reel that we got for the rest of the production. After assembling 60 iCEBreakers with the new green LED we were ready to test them. To our surprise the LED were ultra bright, way too bright. It turns out we made a mistake when placing the order for the LED and they were 200 mcd (millicandela) at 4 mA instead of 40 mcd at 20 mA.

“We were able to remedy the problem by ordering a new reel of different green LED, it only delayed us by three days, but still… Now the boards have less retina burning LEDs and everything is back in business. None of the boards going out to backers will have the bright LEDs. We will continue production and fulfillment, so more and more of you should be getting shipment notifications as we continue packing orders.”

The full update, available on the project’s Crowd Supply campaign page, details that 240 boards were produced and 182 shipped during July.

Clifford Wolf Releases Verilog Implementations for RISC-V Bitmanip

Clifford Wolf has published Verilog implementations for all currently proposed bit manipulation (bitmanip) instructions, as part of the RISC-V Bitmanip Extension Working Group’s efforts.

“I wrote Verilog reference implementations of all proposed RISC-V bitmanip instructions,” Clifford announced on Twitter. “I’m pretty happy with the results. The cores are permissively licensed under ISC licence.”

The Verilog implementations can be found on the RISC-V Bitmanip Extension GitHub repository, alongside versions 0.90 and 0.91 of the proposals plus a frequently-updated draft copy, build scripts, a test suite, and reference C models with related formal proofs.