El Correo Libre — Issue 2

ORConf 2017 group photo © Craig Shaw Photography.

Registration has opened for ORConf 2018 and presentation proposals are invited, while we release another newsletter packed with developments from across the community.

Welcome to the second issue of the LibreCores newsletter, featuring topics including the Xilinx ACAP launch, an open audio controller IP, FuseSoC 1.8.1, the RISC-V Barcelona workshop, APIO 0.3.2, and the generation of a simple design for a Coolrunner-II XC2C32A using only open source tools.

Of course, the biggest news for us — and, yes, we may be just a little biased — is that preparation for ORConf 2018 is now well under way, with registration having opened up and the call for presentation proposals gone out. This year the Gdansk University of Technology has kindly offered to host us and we’re looking forward to holding the first ever ORConf in Poland.

The annual conference for open source digital, semiconductor, and embedded systems designers and users will take place over 21st — 23rd September and once again feature three days of high quality talks plus a conference dinner, and thanks to the generous support of sponsors is free to attend. Speaking of which, should you or the organisation that you represent be interested in sponsoring the conference, please do get in touch to find out details of the available sponsorship packages.

In the meantime, here are a few useful links:

Schedules from recent years for an idea of what to expect:

We look forward to receiving your presentation proposals and seeing you in Gdansk in September!

Andrew Back, FOSSi Foundation Treasurer & Director

Have feedback or news for inclusion in a future newsletter? Please send this to ecl@librecores.org. Subscribe to get El Correo Libre direct to your inbox.

This Month in Free and Open Source Silicon

Engineer Robert Ou has achieved a major breakthrough this month, demonstrating a functional ‘blinky’ test programming running on a Xilinx CoolRunner-II XC2C32A using nothing but open-source tools.

Robert’s ‘blinky’ experiment started with a several-kilohertz blink viewable only on an oscilloscope, before being refined into something visible on the board itself. “You need the absolute latest yosys git head and this code here,” he writes of the experiment. “Unfortunately there is no documentation at all. Good luck!”

The Xilinx CoolRunner-II family has previously been limited to programming via a proprietary toolchain.

Andrew Wygle has released a Lattice ice40 LM development board design, smolfpga, under a permissive licence and building on the work of Luke Valenty.

“Smolfpga is a development board for the Lattice ice40 LM series of FPGAs. Its primary purpose in life is to facilitate the development of support for the LM family in the icestorm toolchain,” Andrew writes of his GPL-licensed design. “Smolfpga is heavily inspired by the TinyFPGA series of boards by Luke Valenty, and some of the footprints and schematic symbols used in this project were borrowed from the TinyFPGA B2 board under the GPLv3.”

Full details on the smolfpga design can be found on Andrew’s GitHub repository.

SinMai Electronics’ Daniel Ogilvie has written on what he jokingly describes as an “afternoon diversion,” designing a novel microprocessor from scratch, based on his experience developing the PT13 core.

“I decided to design my own minimal microprocessor for those simple tasks such as I2C control of peripherals, or simple control interfaces such as digital encoders and character LCD displays,” Daniel explains. “I loosely based the design on my favourite, the 6809, but soon started stripping it bare, finally managing to squeeze a workable processor into less than 400 logic elements (LEs — basically a 4-input look-up table followed by a programmable flip-flop — the building blocks of FPGAs), allowing it to fit in the smallest of FPGAs, or allow multiple instantiations in the same FPGA.

“Designing the PT13 was a lot of fun, and very different from my day job, which is video processing. OK, there are a zillion microprocessors out there running at 600 MHz and able to make you tea whilst reading you a bedtime story, and all for a couple of dollars. But designing the PT13 was a throwback to the days when you made your own audio amplifiers or AM radio. Probably dozens of projects have “PT13 Inside”, trundling away, reading and twiddling bits.”

Daniel’s full piece can be read over on the EDN Network, while more information on the PT13 core is available from the SingMai website.

Efabless chief executive officer Mike Wishart, meanwhile, has written more generally on the topic of the need for “open innovation,” working beyond simple open source software in a collaborative and sustainable fashion.

“We can all agree that open source revolutionised the software industry. The effect has been profound on every segment from enterprise software to search and social networking,” Mike writes. “But it wasn’t always that way. The late Jim Ready, founding father of embedded open source software, told me once that his early prospects told him that open source wouldn’t fly because they wouldn’t trust their code to a bunch of teenagers in some far-off part of the world. Well, guess what? Embedded open source software not only works; most our world runs on it today.

“That said, the real story is open innovation, of which open source licenses are simply one part. Open innovation means looking outside traditional corporate silos to harness the collective knowledge of a global community of developers and using that community to create new and transformative things. Open innovation in software is enabled by many things: GitHub, app stores and crowdsourcing platforms like Topcoder being just a few. Once enabled, though, the innovation potential of this crowd is mind boggling.”

Mike’s full feature can be read over on EE Times.

Rudolf “Rudi” Usselmann, one of the founding contributors to the OpenCores project, has released a new audio controller IP core dubbed the Multi Protocol Audio Controller, or MPAC.

“Some 17 years ago, I wrote the AC97 IP core at OpenCores, and thought it was time to provide an update,” Rudi writes in his announcement on the LibreCores mailing list. “Some of the features are: Multiple protocol support: I²S, TDM, AC97; 16, 18, 20, 24 and 32 bit sample size support; up to 16 output channels; up to 16 input channels; flexible data alignment and packing; configurable internal buffers; external DMA engine support; AXI Light interface for registers; AXI Streaming interface for data.

“This is just the first release, and is missing AC97 support, which will be added shortly. I will also provide an AXI based DMA engine to go with this core.”

The core is available now on Rudi’s GitHub repository, under a custom licence which allows for redistribution and use in source and binary forms with or without modification so long as the copyright notice remains intact.

Ken Shirriff, meanwhile, has published a great write-up on implementing the FizzBuzz algorithm on an FPGA, using the Xilinx Spartan-6 based Mojo development board and Verilog.

A common sight in programming aptitude tests, FizzBuzz requires a program that prints the numbers one through 100 inclusive but replaces multiples of 3 with ‘Fizz,’ multiples of 5 with ‘Buzz,’ and multiples of both with ‘FizzBuzz.’ “Implementing FizzBuzz in digital logic (as opposed to code) is rather pointless,” Ken admits, “but I figured it would be a good way to learn FPGAs.

“Personally, I was very reluctant to try out an FPGA because they seemed scary and weird. While there is a learning curve, FPGAs aren’t as difficult as I expected. If you’re interested in new programming paradigms, FPGAs will definitely give you a different perspective. Things that you take for granted, such as performing operations in sequence, will move to the foreground with an FPGA. You can experiment with high degrees of parallelism. And FPGAs will give you a better idea of how digital circuits work.”

Ken’s FizzBuzz core is available under the MIT Licence on his GitHub repository, though he is keen to warn that as a beginner to FPGAs “I certainly wouldn’t get the FPGA job if FizzBuzz was used as an interview question, though!”

Educational electronics specialist AlhambraBits has officially launched its IceZum Alhambra board, based on the Lattice iCE40HX1K-TQ144 FPGA and boasting full compatibility with Clifford Wolf’s open-source IceStorm toolchain.

“This board is about exploring the open source side of the FPGAs. We know that there are more powerful FPGAs. We know that the are very amazing software tools that can do a lot of stuff… but they are not open source,” its creators write of the board. “So, if you like the freedom too, this board is for you.”

Designed around the familiar Arduino Uno layout, the board includes a Lattice iCE40HX1K-TQ144 FPGA, 12MHz MEMS oscillator, 20 5V input/output pins, eight 3.3V input/output pins, USB connectivity through an FTDI 2232 chip, eight on-board general-purpose LEDs and two general-purpose push-buttons, four analogue inputs via an I²C bus, and various hardware protections against short circuiting, polarity reversal, and other damaging ‘learning experiences.’

The board is available to buy now from Tindie.

FPGA specialist Xilinx has announced a new product category, the Adaptive Compute Acceleration Platform (ACAP), which could play host to future generations of open silicon designs for central and acceleration processors.

“This is a major technology disruption for the industry and our most significant engineering accomplishment since the invention of the FPGA,” claims Victor Peng, president and chief executive of Xilinx. “This revolutionary new architecture is part of a broader strategy that moves the company beyond FPGAs and supporting only hardware developers. The adoption of ACAP products in the data center, as well as in our broad markets, will accelerate the pervasive use of adaptive computing, making the intelligent, connected, and adaptable world a reality sooner.”

An ACAP, Xilinx explains, is a multi-core heterogeneous compute platform which can be adjusted to particular workloads at the hardware level on-the-fly and which, the company claims, offers considerable boosts in both raw performance and performance-per-watt (PPW) compared to fixed CPU or GPU systems. Each ACAP includes a next-generation FPGA with distributed memory, programmable DSP blocks, a multicore system-on-chip, one or more software programmable and hardware adaptable compute engines, and a network-on-chip (NoC) interconnect.

Xilinx has pledged to launch the first Acap, codenamed Everest, early next year, with more information available on the company’s official website.

The RISC-V open instruction set architecture has had a busy start to the year, beginning with an interesting write-up from Semiconductor Engineering’s Ann Steffora Mutschler.

Discussing the ISA and its implementations both present and proposed with a range of semiconductor and open silicon luminaries, Ann’s piece discusses a number of the benefits it brings to the table — in particular the fact that it is open and, in the words of UltraSoC chief executive Rupert Baines, “in effect, everyone who wants one has an architecture licence.”

Ann’s conclusion, however, warns of “uncertainty and new challenges because one implementation of the architecture can be significantly different from another, the the point where IP developed for one version may not work the same for another,” although ends on a positive note of “plenty of momentum and room for growth on its own and in conjunction with other vendors’ processor cores.”

One particular area of interest for the Free and Open Source Silicon Foundation itself, though, is Ann’s mention that “new licensing models may be required for the design tools” — the very reason why the Free and Open Source Silicon Foundation put together a licensing committee which investigates the applicability of existing open source and free software licences to register transfer level (RTL) code and, where required, works on creating new licence types.

The full feature is available on Semiconductor Engineering now.

Registrations have opened for the RISC-V Workshop in Barcelona, a three-day community event with a fourth day dedicated to meetings of the RISC-V Foundation’s technical and marketing committees.

Registration is now open for the RISC-V Workshop in Barcelona, co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) May 7–10, 2018. The event will be sponsored by NXP and Western Digital,” writes the RISC-V Foundation of the event.

“As with past workshops, this event will bring together the RISC-V community to share RISC-V activities underway around the globe, and build consensus on the future evolution of the instruction set.”

The three public days begin with a tutorial and demonstration session on Monday the 7th of May 2018, two presentation days on Tuesday and Wednesday following, and the invitation-only RISC-V Foundation meetings on the Thursday. Networking opportunities, parties, demonstrations, and tours of the Barcelona Supercomputing Centre, housed in a former chapel, are also included in the schedule.

More information is available from the RISC-V Foundation website.

Even as it prepares for the Barcelona workshop, the RISC-V Foundation has found time to post a round-up of the RISC-V-related news to come out of the Embedded World 2018 conference held in Nuremberg, Germany, earlier this year.

“Embedded World 2018 showcased the incredible momentum of the RISC-V ecosystem. Throughout the show the RISC-V Foundation booth — which featured pods from member companies Antmicro, GreenWaves Technologies, Imperas, Syntacore, UltraSoC and VectorBlox — was packed with attendees buzzing about the exciting announcements, solutions and demos from member companies,” the Foundation writes in its round-up.

The write-up of the event also includes video interviews conducted by Embedded Computing Design’s Rich Nas with the RISC-V Foundation and member companies Antmicro, Imperas, GreenWaves Technologies, UltraSoC, and VectorBlox.

The full write-up is available on the RISC-V Foundation blog.

The RISC-V compatibility pool grows with the news that both Debian and Fedora Linux have active RISC-V ports, with Manuel Montezelo and Richard W.M. Jones offering behind-the-scenes looks at the process for their respective distributions.

“We’ve been working in the last few weeks to do a (second) bootstrap of Debian for RISC-V, and after a few weeks of hard work it is now bootstrapped and has been imported into the Debian infrastructure, in particular, debian-ports,” explains Debian’s Manuel Montezelo. “All packages that are uploaded to the archive by any of the hundreds/thousands of contributors are attempted to be built for each one of the architectures/ABIs almost immediately, so having ‘riscv64’ [64-bit RISC-V] as a Debian architecture is a quite critical step. This means that, from now on, anybody can download .deb packages targeted for riscv64 (rv64gc, to be precise) which compile successfully, often only a few hours after being uploaded to the archive.”

“The first question I’m usually asked is: How do you bootstrap Linux on a new architecture? We were lucky that most of the seriously hard work — adding support to the kernel and the compiler — was already done by the RISC-V Foundation about two years ago,” writes Fedora’s Richard W.M. Jones. “However there’s still the rather large problem that a .riscv64.rpm cannot be built using rpmbuild, because Fedora’s RPM does not support cross-compilation, so we must use a Fedora/RISC-V machine. That led to another problem, of course: Fedora/RISC-V didn’t exist.”

Manuel’s write-up is available on his personal Debian page, while John’s is published on LWN.net.

John L. Hennessy and David A. Patterson have been granted the A.C.M. Turing Award for their work on the concept of reduced instruction set computing (RISC), as codified in the publication Computer Architecture: A Quantitative Approach.

With David having worked on the team at Berkeley which coined the term RISC and developed the RISC-1 microprocessor prototype that would become Sun’s SPARC architecture, it’s no surprise to hear that he acts as vice chair of the board at the RISC-V Foundation where he continues his work. John, meanwhile, left his role as the president of Stanford University in 2016 and now acts as chair of the board of Google parent Alphabet among other roles.

“ACM initiated the Turing Award in 1966 to recognize contributions of lasting and major technical importance to the computing field,” says ACM President Vicki L. Hanson. “The work of Hennessy and Patterson certainly exemplifies this standard. Their contributions to energy-efficient RISC-based processors have helped make possible the mobile and IoT revolutions. At the same time, their seminal textbook has advanced the pace of innovation across the industry over the past 25 years by influencing generations of engineers and computer designers.”

More information is available on the award website.

Free and Open Source Silicon Foundation director Olof Kindgren has launched FuseSoC 1.8.1, the latest release of the Hardware Description Language (HDL) package maintainer and build toolset.

“With great features come great bugs. FuseSoC 1.8 had a lot of new functionality but it also has some shortcomings. Some of it was intentional. For both the library support and CAPI2 I wanted to push out an early version with the most important functionality, test the waters and add the missing pieces later,” writes Olof of the latest release. “(Un)fortunately both these features turned out to be really really good and I came to depend on them immediately. This made it more important to make sure they were useful as I don’t want to use the old ways anymore. After some post-release patching I’d say things are in much better shape, so it made sense to do a new release with these things fixed. Therefore I present FuseSoC 1.8.1. It’s like 1.8, just a little better.”

The new release includes a synchronisation type flag for the configuration file, CAPI2 fixes with additional tools, and a bash completion script, while also disabling the write-by-default behaviour of the log file.

More information on FuseSoC 1.8.1 can be found in Olof’s announcement post, while the code and installation instructions are available on his GitHub repository.

Apio, FPGAwars’ experimental micro-ecosystem focused exclusively on use with open field-programmable gate arrays, has reached version 0.3.2 in its stable branch.

Built on top of platformio but with a tight focus on open FPGA platforms, Apio serves as the backend for FPGAwars’ Icestudio graphical editor. Designed to operate cross-platform, the Verilog-focused utility is described as a “multiplatform toolbox” featuring “static pre-built packages, project configuration tools and easy commands to verify, synthesize, simulate and upload your verilog designs.

“Apio appeared as a need to unify and simplify the use of the main open source tools for open FPGAs Icestorm and Icarus Verilog. This became very useful for the verilog developers as a CLI and for projects like Icestudio as a back-end. We want to spread the open FPGA knowledge and tools to everyone (eg: verilog tutorial). Simplifying the setup time would help to focus on the content, improve workshops performances, etc. In short, reduce the entry barrier to new users.”

Apio 0.3.2 is available now from the FPGAwars GitHub repository.

Finally, ZipCPU creator Dan Gisselquist has begun the process of formal verification of the core, publishing each bug found as it pops up in an effort to demonstrate the value of formal methods in CPU errata detection.

“At this point in the game, I’ve already formally proven all of the components of the ZipCPU. What remains is to prove the CPU itself,” Dan writes. “So here’s my question: How many bugs would you expect to find in a ‘working’ soft-core CPU? One? Ten? Twenty? One hundred? Shall we count? I propose keeping a running log of the bugs I find in the ZipCPU while using formally methods. Perhaps this log will help to convince you the value of formally methods, perhaps not. Either way, I’ll keep it accurate to the information I discover.”

Since beginning the process in early April, Dan has found 11 individual bug categories — ranging from issues with its debug infrastructure to bus errors halting the CPU — along with three bugs in the formal properties themselves.

“I intend to update this page as I find more bugs, so that we can have a full accounting of how many ‘bugs’ formal methods might find in a ‘working’ CPU,” Dan explains. “Once finished, the updated ZipCPU code will be pushed to its GitHub repository.”

You can follow along with Dan’s verification on the ZipCPU blog.

Have feedback or news for inclusion in a future newsletter? Please send this to ecl@librecores.org. Subscribe to get El Correo Libre direct to your inbox.