El Correo Libre Issue 20

Published in

LibreCores

15 min readOct 8, 2019

ORConf2019 A Resounding Success

ORConf 2019 has come and gone, and thanks to the speakers, attendees and organizers, it was another successful event for all. The superb venue of autumnal Bordeaux provided the backdrop to 3 days of impressive talks from the ever broadening church of the open source digital design scene.

Another full house of locals and folks from across the globe meant the buzz was constant throughout the weekend. We’re always pleased by how many new faces we see, and also those who keep on coming back to ORConf each year to catch up with us all. Our local hosts, Guillaume and Benjamin of Hiventive, ensured the event was well catered and we were treated to a tour de force of the region’s culinary delights at each break.

As Olof Kindgren mentioned in his intro, this year was dubbed the year of the foundations focused on furthering open source silicon and IP, and we had no fewer than four represented (including the FOSSi Foundation, of course!) on Friday and Saturday.

Andrew Katz and Javier Serrano took us through their work on the CERN Open Hardware Licence (OHL) v2 which is looking like the best-thought-through open source licence applicable to digital designs yet.

The VHDL crew are growing in numbers and we witnessed that this year at ORConf with a larger number of VHDL talks than ever before. Closing out Friday was an update on the impressive ASICone efforts.

Saturday saw Philipp Wagner giving us his update on the enormous amount of progress made by the cocotb maintainers over the past 12 months since ORConf in Gdansk, as well as hearing from Rick O’Conner on the work of the recently-founded Open HW Group. Staf Verhaegen showed persistence pays off, with his tape outs out using entirely open source back-end flows, some 0.35um chips bringing his open source Retro-uC chip project closer to a reality. The multitalented Stafford Horne also updated us on what the OpenRISC project — the conference’s namesake — has been up to lately.

The afternoon saw a flurry of talks on the status of the open source FPGA tooling efforts. This is one of the most impressive areas in recent years we’ve been lucky enough to have a front-row seat for it at ORConf.

We welcomed more familiar faces on Sunday with Dan “ZipCPU” Gisselquist updating us on his fun with AXI and large FPGA vendors, Alan Wood with a roadmap for the myStorm FPGA suite, Frank from ETH Zurich whirlwinding us through the PULP projects incredible number of tape-outs, Jörg Mische on the challenges of timing-predicable cores and finally Staf again to round out the weekend asking us to reconsider the HDLs we use.

Saturday’s dinner was well enjoyed by all at Chez Alriq on the banks of the Garbonne in perfect weather. A big thank you to Google for sponsoring the evening!

As always there are many people to thank for this event. First of all our sponsors for helping cover the costs and to make it free for everyone to attend — thank you to our headline sponsor Western Digital and to our major sponsor Open HW Group and to all of our sponsors, and professional ticket buyers — a big thank you! Without your support the event wouldn’t be as inclusive or easy going.

Also a big thank you to those who joined us and presented and for those who joined and got involved in your own way, it’s enormously satisfying for us at the FOSSi Foundation to see everyone enjoying themselves in the company of other like-minded folks.

Finally another thank you to our hosts, Guillaume and Benjamin from Hiventive, a lot of work goes on behind the scenes for them to arrange all of this for the three days of ORConf.

A reminder that should you want to join us for similar conferences we have FOSSistanbul early next year and Latch-Up at Easter. There will be announcements via the usual channels about those shortly.

Hopefully we’ll see you at a FOSSi Foundation event in the new year!

-Julius Baxter, Director, Free and Open Source Silicon (FOSSi) Foundation

RISC-V Foundation Announces RISC-V Soft-Core Contest Winners

The RISC-V Foundation has announced the three winners of its security-focus soft-core contest, which sought to encourage implementations of the open instruction set architecture which focused on improving security and attack resistance.

First place in the contest went to Changyi Gu, with 78 out of a possible 100 from the scoring metrics which included performance and economy of FPGA resources, for a RISC-V core dubbed Rattlesnake. The core included what the Foundation describes as “a sophisticated dirty bit method” to tag suspicious consecutive writes and mark that memory as non-executable.

Second place went to Featherweight RISC-V (FWRISC-S) by Matthew Ballance, with 73/100 points, which adds a data protection system to protect defined memory until the next core reset. Matthew’s design was further praised for its compactness.

Third place was taken by Jörg Mische’s RudolV design, which combines region-based memory protection with detection of suspicious write activity and scored 69/100.

A special mention went to Alexey Baturo, Anatoly Parshintsev, Fedor Veselovsky, Igor Chervatyuk, and Sergey Matveev, who competed as the Ecco Team and created a core which implements memory tagging using a pseudorandom generation. The entry wasn’t eligible for a prize, unfortunately, as it was implemented on a different FPGA development board than the contest’s target.

More information is available on the RISC-V Foundation blog post.

1st CLaaS Project Gets a Boost from Google’s Summer of Code

Redwood EDA’s Steve Hoover has been asked by Google to pen a retrospective look at the work carried out on the 1st CLaaS custom-logic-as-a-service platform under the Google Summer of Code programme — and claims that improvements made in partnership with Ákos Hadnagy have pulled down the barriers to its use and “helped open the floodgates” for free and open source silicon.

“So, why is coding and sharing circuit models any different from sharing software? Three reasons: implementation details; access to software, access to hardware,” Steve writes. “My personal contributions to this open source silicon movement stem from my startup, Redwood EDA. We directly target problem #1 by providing tools that support advanced (yet simpler) circuit modelling techniques. And, to address #2, we make all of our software freely available online for open source development. But neither open source EDA nor the efforts of my startup had been able to noticeably impact problem #3, access to hardware.

“In the past few years, cloud providers have begun incorporating FPGAs into their datacentres. These are available to anyone with an internet connection and a credit card, bundled with industry-class EDA software, on a pay-per-use basis. Wow! This is the solution to hardware access! An open source developer can provide not only their hardware model but also the platform for which their model was designed. A user can download and go, just like they can with software! …in theory. So here’s the rub. The learning curve for cloud FPGA platforms has been way too high for the open source community to latch on.”

The answer comes from a partnership with GSOC student Ákos Hadnagy on developing a webserver framework for FPGAs: 1st CLaaS. “Very simply, 1st CLaaS wraps a developer’s custom FPGA logic as a microservice. Standard web protocols can be used to stream bits to and from this logic, and platform details are hidden by the framework,” says Steve. “So there is no longer anything standing in the way! Hobbyists can build and share hardware, and open source silicon can thrive. Just imagine the disruption this will have on the industry, which is currently driven by corporate giants. And with easy web integration, the opportunity and demand for hardware acceleration should rise, and we could start to see some interesting new capabilities on the web that were not imaginable until now.”

Steve’s full post is available on the Google Open Source Blog now, while 1st CLaaS can be found on GitHub under the BSD 3-Clause licence.

Inspur Releases Full-Stack Artificial Intelligence Framework for FPGAs: TF2

Inspur Group has announced the release of a full-stack artificial intelligence framework designed for running workloads on FPGAs, and it’s making it available under the permissive Apache 2.0 licence.

“The deployment of AI applications covers the cloud, the edge, and the mobile end, and has highly diverse requirements. TF2 can greatly improve the efficiency of application deployment across different ends and quickly adapt to the model inference requirements in different scenarios,” claims Liu Jun, general manager for artificial intelligence and high-performance computing at Inspur Group. “AI users and developers are welcome to join the TF2 open-source community to jointly accelerate the deployment of AI applications and facilitate the implementation of more AI applications.”

The TF2 framework is split in two. Its first half is a model optimisation and conversion tool designed to compress, prune, and quantise model data from commonly-used deep-learning frameworks; its second half is a runtime engine designed to convert these optimised models into FPGA target running files which offer boosted performance and efficiency — up to 12.8 times the speed of a general implementation on the same hardware, the company claims. A software-defined reconfigurable chip architecture is also included, with the aim of supporting the development of convolutional neural network models with easy porting from other tools including Transformer and LSTM.

The TF2 framework is available now on the company’s GitHub repository, under the Apache 2.0 licence.

OpenPOWER Foundation Releases Fire and ICE OMI Implementations

IBM, via the OpenPOWER Foundation, has fulfilled its promise to release permissively-licensed implementations of Open Memory Interface (OMI) hosts and devices in order to promote use of its freshly-opened OpenPOWER instruction set architecture.

At the time of the company’s original announcement that OpenPOWER, originally developed as the PowerPC architecture by Apple, IBM, and Motorola under the AIM partnership, the OpenPOWER architecture was released as free and open source silicon back in August this year. At the time, the Foundation stated that IBM was donating reference implementations for the Open Memory Interface (OMI) — which are now available for the first time.

ICE is a reference implementation of an Open Memory Interface device with two DDR4 memory ports; Fire, meanwhile, is a host design which can be used to test an OMI device, including ICE. Both have been released through the OpenCAPI Consortium using the Apache 2.0 licence.

Fire and ICE are available now from their respective GitHub repositories.

Antmicro Releases Fast Versatile DMA Controller: FastVDMA

Antmicro has announced the release of a fast and versatile direct memory access controller dubbed, unsurprisingly, FastVDMA.

“One of the main motivations leading to the design of an open source DMA controller was the lack of portable open source alternatives to proprietary controllers provided by FPGA vendors,” Antmicro claims. “This situation leads to a reduction in the reusability of DMA-based designs into different contexts when adopting multiple kinds of platforms, since DMA solutions tend to be tightly integrated with vendor-specific toolchains and IP. As a result, a non-negligible part of the work required in creating designs that implement proprietary DMA controllers, ends being highly platform-dependent and less useful to developers using other platforms.

“At Antmicro, we strongly advocate cross-platform and reproductible solutions to our customers, and are often the first to identify both immediate and long-term vendor lock-in constraints. The integration of FastVDMA with portable SoCs such as LiteX, would solve the portability and platform-dependence of any DMA-based designs, and so allow for more engineering freedom in our FPGA projects. With the rise of open source ISAs (like RISC-V and POWER) and the proliferation of openly available FPGA softcores implementing them (just take a look at the RISC-V cores list Antmicro is helping maintain), vendor-neutrality and portability — in all aspects — plays an ever increasing role.”

FastVDMA supports AXI4, AXI-Stream, and Wishbone buses as read or write frontends, offering immediate support for memory-to-stream, stream-to-memory, and memory-to-memory transfers, with internal DMA signals handled without care to the chosen interfaces at either end. Created in ChiselHDL — “significantly easier,” Antmicro claims, “compared to the use of standard HDLs such as Verilog or VHDL — the initial implementation uses 455 slices on a Zynq 7030 FPGA with AXI4-Lite configuration port, AXI-Stream input, and AXI4 output interface.

“The implementation of the FastVDMA controller as described above was verified on hardware achieving an average throughput of 750MB/s, while being clocked at 250MHz, and reached 330MB/s at 100MHz under the same workload,” Antmicro says. “Both these tests were performed in a Memory-Stream-Memory configuration using two controllers configured with AXI4 and AXI-Stream buses. The first controller reads data from memory and sends it out via an AXI-Stream interface, while the second receives the stream and writes the data received to a second buffer in memory.”

More details are available on the Antmicro blog, while the code is available in Antmicro’s GitHub repository under the MIT Licence.

Renode 1.8 Brings Multi-Core GDB Support, New RISC-V Platforms

Antmicro has also announced the release of Renode 1.8, the latest version of the company’s open-source multi-node simulation framework, bringing with it initial multi-core GDB support and new RISC-V platforms.

“Before version 1.8 each CPU core had to be exposed with a separate GDB server. But that simplification did not resemble real-life scenarios, in which you’d expect to be connecting just one GDB instance even for a multi-core device,” explains Antmicro of the new multi-core functionality. “Now, after important API changes and expanding Renode’s GDB remote protocol support by implementing a bunch of new commands, GDB server is started on a machine level instead of a CPU level and is able to handle multiple cores at once.”

The new release also brings support for the RI5CY-based VEGAboard, popularised by a US giveaway, and the Digilent Arty with LiteX and VexRiscv. LiteX support in general has been upgraded with SPI, control, status, SPI flash, and GPIO port peripheral models, while support for the 32-bit Minerva RISC-V soft CPU is included.

Finally, Renode 1.8 adds new co-somulation capabilities, building on those added in release 1.7.1. “By adding an EtherBone bridge model to the platform, you are now able to connect a simulation running in Renode to peripherals connected to a WishBone bus on a real FPGA. This allows you to develop software in a well-controlled Renode environment, while using accurate HDL models you already have. We have also added an EtherBone bridge demo based on Fomu, an open, tiny FPGA development board that fits into a USB port, with instructions on how to run it locally.”

More information is available from Antmicro’s announcement, and the 1.8 release has been tagged on GitHub.

Matthew Venn Completes Open Source FPGA Tool Flow Video Series

Symbiotic EDA’s Matthew Venn has uploaded the final section of his three-part video series looking at the open-source FPGA tool flow, offering an introduction to those as-yet unfamiliar.

The first video, uploaded early last month, introduced the Yosys Open Synthesis Suite, answering the question “how does simple logic get synthesised into something we can map onto the logic available inside a Lattice iCE40 FPGA?” This was followed a week later by a second, looking at how nextpnr takes the Yosys netlist and places and routes the logic on the FPGA itself.

The final video in the series looks at how the ASCII representation of the configuration bits are converted to a binary file and programmed onto the FPGA — as well as a brief look at going in the opposite direction. It also takes a look at some of the FPGA development boards compatible with an open-source toolchain, including the iCEstick, iCEbreaker, TinyFPGA, and Alhambra.

All three videos are available now on the Symbiotic EDA YouTube channel.

Professor Onur Mutlu Releases Full Computer Architecture Course Lectures

ETH Zurich Professor Onur Mutlu has announced the release of a full collection of videos, slides, and course materials used in the lectures for the Spring 2019 undergraduate digital design and computer architecture course.

“The class provides an introduction to the design of digital circuitry. The class covers the basics of the technical foundations of gates. An introduction to hardware description languages and their use in the design process follows,” Onur’s course description reads. “This class will be your first approach to Computer Architecture. You will study the design of digital circuits in order to: understand the basics; understand the principles (of design); understand the precedents.

“Based on such understanding, you will: learn how a modern computer works underneath; evaluate trade-offs of different designs and ideas; implement a principled design (a simple microprocessor); learn to systematically debug increasingly complex systems; hopefully develop novel, out-of-the-box designs.”

Slides and video for each lecture are available now on the ETH Zurich Safari system, available for open access, while the videos are also available as a YouTube playlist.

Xilinx Announces Vitis Development Platform, Built on Open Tools

Xilinx has officially announced the Vitis development platform, through which it hopes to tempt software engineers and artificial intelligence (AI) scientists into the field of FPGA development — and it’s used open source tools as its base.

“With exponentially increasing compute needs, engineers and scientists are often limited by the fixed nature of silicon,” says Victor Peng, president and chief executive officer of Xilinx. “Xilinx has created a singular environment that enables programmers and engineers from all disciplines to co-develop and optimise both their hardware and software, using the tools and frameworks they already know and understand. This means that they can adapt their hardware architecture to their application without the need for new silicon.”

The Vitis platform is designed to stack up, beginning with a target platform based of a Xilinx development board with preprogrammed input/output. The Vitis Core Development Kit, which includes the Xilinx open-source runtime library and development tools, provides a toolchain with compilers, analysers, and debuggers; and the final layer is a collection of some 400 open-source libraries designed to be accelerated on the FPGA and callable via a standard API.

The Vitis platform also includes domain-specific architectures, starting with Vitis AI for acceleration of artificial intelligence frameworks including TensorFlow and Caffee and to expand with Vitis Video for decoding using FFmpeg.

Xilinx claims that the Vitis platform is an alternative to “imposing a proprietary development environment,” but while it has agreed that the libraries including the Xilinx Runtime Library will be open-source it has not yet committed to making the whole platform available under the same terms; instead, it simply says it will be “free for Xilinx boards.”

More information can be found on the official website.

MIPI Announces Open Access to Nine Debug and Trace Specifications

The Mobile Industry Processor Interface (MIPI) Alliance has made the surprising move to release nine debug and trace specifications under open access terms for the first time, including its most recently-released SneakPeek Protocol v2.0.

“Opening up access to MIPI debug and trace specifications will foster a more standardised debug environment, improving development processes and quality in and beyond the mobile device industry,” says Joel Huloux, chair of MIPI Alliance, of the move. “In addition to allowing more developers to use the specifications, this step will strengthen the ecosystem, leading to broader interoperability and a richer development environment.”

The nine specifications made available for open access are: MIPI System Software-Trace, specifying a universal data format for the transmission of debug and trace information; MIPI Narrow Interface for Debug and Test, a specification which allows for debug and testing via functional ports on finished devices; the MIPI System Trace Protocol, a base protocol for application-specific trace functions; MIPI High-Speed Trace Interface and the related MIPI Parallel Trace Interface, for the exportation of trace data; MIPI Gigabit Debug for USB and MIPI Gigabit Debug for IP Sockets; and the new MIPI SneakPeek Protocol v.20, a standard communications protocol for debug and test applications and which includes MIPI TinySPP for low-bandwidth or high-latency interfaces.

All nine standards can be accessed now via the MIPI website.