ORConf 2019 Presentation Videos Now Available
Those who were not able to attend ORConf 2019, or those who were but need a refresher on everything that happened, will be pleased to hear that videos for all 42 presentations at the event are now available on the FOSSi Foundation’s YouTube Channel.
Presentations given at the event and captured for posterity include, but are most certainly not limited to, a look at open-source formal verification from Pepijn de Vos, an introduction to the LibreCores continuous integration (CI) pipeline from Oleg Nenashev, Jeremey Bennet on the release of the open Embench 0.5 benchmark for Internet of Things (IoT) projects, an update on the OpenRISC projects from Stafford Horne, and an introduction to the Open Source SCR1 core by Ekaterina Berezina.
Presentations from FOSSi Foundations directors are also included, with Olof Kindgren offering a welcome keynote while Stefan Wallentowitz provides an introduction to the Foundation itself.
All videos are available now, sorted into chronological order, in a dedicated YouTube playlist.
Observer Brings RISC-V Cores to Bear on Heterogeneous Sensor Aggregation
Free and Open Source Silicon Foundation (FOSSi Foundation) director Olof Kindgren has released a new tool designed to simplify the handling of heterogeneous sensors with differing protocols on FPGA platforms: Observer.
“Implementing the logic for sensor communication, post-processing and format conversion directly in an FPGA can quickly become very time-consuming,” Olof explains. “This is a task much better suited for a CPU. On an FPGA it’s no problem to add a soft CPU, but the more sensors that are connected to the CPU, the harder it will have to keep up with any real-time aspects of the data collection.
“Observer deals with this by attaching a CPU to each sensor interface that handles all bring-up and data collection from the sensor and produces a well-formed data packet which is then forwarded to a common aggregation node. By using the small SERV RISC-V CPU it is possible to do this without costing much resources.
“This has a number of benefits,” Olof continues. “Data collection and post processing from each sensor can be done completely independent of the others. It allows for power savings by doing complex data reduction very close to the sensor and allowing unused nodes to shut down when not in use. Depending on the complexity of the sensor interfacing or post processing, each node can independently decide to do this using a couple of lines of assembly code, a bare-metal C program or even run a RTOS such as Zephyr.”
Observer is available now on Olof’s GitHub repository.
lowRISC Partners with Google, Western Digital for OpenTitan RoT Project
The lowRISC community interest company (CIC) has announced its stewardship of a new project, developed in partnership with organisations including Google and Western Digital, to bring the Ibex core to root-of-trust (RoT) creation and verification: OpenTitan.
“We believe collaboratively developed open source silicon designs provide the flexible, cost effective base needed for future generations of secure hardware products,” explains Alex Bradbury, lowRISC chief technology officer. “The lowRISC not-for-profit structure combined with full stack engineering capabilities in-house, enables us to manage high quality projects like OpenTitan, and we look forward to developing this partnership and new ones in the future.”
“Customers are asked to put faith in proprietary hardware RoT chips for their mission-critical systems without the ability to fully understand, inspect and therefore trust them,” adds Dominic Rizzo, OpenTitan lead at Google and lowRISC’s OpenTitan project director. “By creating OpenTitan with the broader hardware and academic community, we can leverage the experience and security principles used to create Google’s own Titan chips to make hardware RoT designs more transparent, inspectable, and accessible to the rest of the industry. Security should never be built on opacity.”
The OpenTitan project is based around lowRISC’s RISC-V Ibex core which was originally developed at ETH Zürich, named as a project partner alongside Google, Western Digital, G+D Mobile Security, and Nuvoton Technology.
More information is available on the OpenTitan website.
Radiona Prepares for ULX3S ECP5 FPGA Dev Board Crowdfunding
Zagreb makerspace Radiona is preparing to launch a crowdfunding campaign for the ULX3S, an open-hardware FPGA development board based on the Lattice Semiconductor ECP5.
“ULX3S is a fully open source, compact, robust, and affordable FPGA dev board equipped with a balanced selection of additional components and expansions,” the Radiona team explain. “Although it was designed primarily as a teaching tool for mastering the principles of digital circuit design, ULX3S incorporates a wide array of features and interfaces that allow it to serve as a broadly useful module for installation in complex devices.
“It comes equipped with onboard Wi-Fi, display, buttons, LEDs, and storage. Flash it with an over-the-air (OTA) update using the Wi-Fi connection or take advantage of the onboard OLED display and buttons to browse the contents of an SD card and select a bitstream. Due to its battery-backed RTC, ULX3S can power down completely and wake up only in response to certain events. This feature makes it perfect for use in low-power applications such as battery-powered remote sensor nodes.
“And if you’re not the low-power type, onboard peripherals like SDRAM, USB, digital video out, onboard FM/ASK antenna, ADC, and DAC make it an audio/video powerhouse for signal processing and synthesis, motor control, and SDR use cases. It can emulate arcade machines and retro computers like the Minimig (Amiga) or modern systems like the F32C (MIPS/RISCV). It has 56 GPIO pins, all routed as differential pairs, and a PMOD compatible pinout, which opens it up to a wide range of expansion options. And if you are just starting out FPGAs, you can use the Arduino IDE to program ULX3S in seconds.”
The ULX3S, which will be available with a choice of ECP5 FPGAs ranging from 84k to 21k LUT count, began life as a collaboration between Radiona and the Faculty of Electrical Engineering at the University of Zagreb in 2016 and owes its PCB design to Electronic Mechanic Aerodynamic Research & Development (EMARD).
More information, and a link to register to be alerted when the crowdfunding campaign goes live, can be found on the Radiona ULX3S Crowd Supply page.
The European Processor Initiative Celebrates its First Anniversary
Officially beginning its activities a year ago, the European Processor Initiative has announced the completion of its first milestones on the road to creating a pan-European research platform for high-performance computing and artificial intelligence — including the release of its Rhea design and commitment to the development of a common platform for the project.
“The first-generation chip family, named Rhea, will include Arm ZEUS architecture general purpose cores and prototypes of high energy-efficient accelerator tiles: RISC-V based (EPAC), Multi-Purpose Processing Array (MPPA), embedded FPGA (eFPGA) and [a] cryptography HW engine,” the project’s latest update explains. “First Rhea chips will be fabricated in N6 technology aiming at the highest processing capabilities and energy efficiency.
“The Rhea chips will be integrated into test platforms, both in workstations and supercomputers in order to validate the hardware units, develop the necessary software interfaces, and run applications. Rhea aims to be the European processor for several experimental platforms towards exascale HPC and future automotive designs.”
The EPI has also confirmed the active development of a common platform which gathers “the global architecture specification (hardware and software), common design methodology, and global approach for power management and security” for both the 2D mesh-based Rhea design and future creations.
The EPI’s updated roadmap sees the launch of the Rhea family in 2021, full IP availability in 2021–222, a second-generation design dubbed Cronos in 2022–2033, then an as-yet unnamed third-generation in 2024 or later should the project be extended beyond its current three-year schedule.
More information is available on the EPI website.
OpenPiton+Ariane Comes to Amazon’s EC2 F1 FPGAs in Release 13
The OpenPiton Project has officially launched Release 13, and it comes with a new feature designed to make it even easier to get started with the heterogeneous OpenSPARC and RISC-V OpenPiton-Ariane research processor: support for running on Amazon’s Elastic Compute Cloud.
“The headline feature of this release is support for running OpenPiton+Ariane in the cloud via Amazon EC2 F1,” explains OpenPiton’s Jonathan Balkind.”Release 13 also offers other bug fixes and improvements that you can see on our GitHub repository.
“We now provide a step-by-step guide in the README of OpenPiton on GitHub which explains how to emulate OpenPiton+Ariane on Amazon EC2 F1 cloud FPGAs. You can make use of our existing release image to test software and firmware, or synthesise your own OpenPiton-based hardware design by following our instructions.”
Full details on the release, including instructions on getting started with an EC2 F1 FPGA instance, are available on Princeton University’s OpenPiton GitHub repository.
Hackaday Superconference Badge Brings RISC-V, Open FPGA Goodies
The Game Boy-inspired badge for the Hackaday Superconference has been unveiled, with a Lattice Semiconductor ECP5 FPGA at its heart — and it includes a dual-core RISC-V SoC on-board.
“The 2019 Hackaday Superconference badge is based on an ECP5 FPGA with 45k LUTs,” explains designer Jeroen Domburg. “It adopts a Game Boy form factor, with eight buttons for user input and a colour LCD screen. Apps can be written in C and copied to the badge via a USB mass storage arrangement. There is also a 40-pin cartridge adapter on the back of the badge and the prototyping cartridges have flash memory to store their own apps which can be loaded when the cartridge is inserted.”
While Jeroen has released the source for the project under the BSD 3-Clause licence for hardware and the GNU General Public Licence 3 for the software source, aside from differently-licensed code brought in from elsewhere, he isn’t the only one: developer David Williams has also released code that FPGA users may find handy.
“The occasion of the release of the Hackaday Superconference 2019 Badge has motivated me to release some FPGA code,” David writes. “There’s an I2C Master, a MIPI Type 2 LCD driver and a MT9V022/034 camera driver.”
More information on the badge itself is available on Hackaday, while the source code and example applications for the RISC-V SoC can be found on Jeroen’s GitHub repository; David’s GitHub page, meanwhile, contains more information about the design of the badge along with the promised FPGA code.
Charles Eric LaForest Releases First FPGA Design Elements Sections
GateForge Consulting’s Charles Eric LaForest has released the first sections from his upcoming book, FPGA Design Elements, which is designed to act as a reference library for commonly-used elements of digital logic design.
“I’m writing an online book: FPGA Design Elements, which provides a reference library of fundamental digital logic design elements,” Charles explains. “Think of it as a hardware analogue to the C Standard Library (“libc”) and its documentation. I’m adding modules as I write them up. [I was] inspired by beautiful books of collections of architectural and mechanical engineering design elements and basic mechanisms.”
The first sections have been made available now, including the “semi-silly example” of a constant value module, a bit reducer, annuller, word reducer, multiplexer, register, and binary adder/subtractor and up/down counter.
The book is being developed in the open: as well as being able to view the current version of the book on Eric’s website, the code is available under the MIT Licence on his GitHub repository — with pull requests and comments welcomed.
CHIPS Alliance Launches New Workgroups for Chisel, Interconnects, Rocket
The CHIPS Alliance, hosted by the Linux Foundation for the creation of a collaborative development and deployment environment for open SoCs, peripherals, and tools, has announced a series of technical milestones alongside the formation of three new workgroups: Chisel, Interconnects, and Rocket.
“The rest of the developer team and I are very excited for Chisel to move to its new home in CHIPS Alliance,” says lead Chisel developer Adam Izraelevitz. “Now with open-source industry backing, Chisel is primed to continue growing its user base, adding new features, and stabilising its infrastructure and ecosystem for industry applications.”
The Interconnects workgroup will be developing the OmniXtend and TileLink projects, the CHIPS Alliance has confirmed, while the Rocket workgroup will do the same for the RISC-V Rocket Chip project.
At the same time, the CHIPS Alliance has announced three key technical milestones: The creation of a portable SoC based on the SweRV Core EH1 released by Western Digital, using FuseSoC and including debug port and support for the Zephyr real-time operating system; the extension of the Verilator simulator to include CMake and Python support for Cocotb; and the launch of a project to add SystemVerilog support to Verilator.
“We want to personally thank Olof Kindgren, Wilson Snyder and Stefan Wallentowitz for their key contribution to open source software development,” says Dr. Zvonimir Bandić, chair of the CHIPS Alliance and senior director of next-generation platforms architecture at Western Digital. “These extraordinary individuals were vital to achieving these milestones. We look forward to further participation in CHIPS Alliance to facilitate the adoption of open architectures.”
More information is available on the CHIPS Alliance website.
nMigen Project Announces Release 0.1 Milestone
M-Labs developer Whitequark has released nMigen 0.1, confirming that the Python toolbox for digital hardware developers should now be usable with no breaking changes planned.
“I’ve released nMigen 0.1rc1! Feel free to try it for your projects; I think all the core parts are quite solid, and I don’t anticipate any breaking HDL or stdlib changes,” Whitequark explains, “unless something truly broken is discovered.”
“nMigen FHDL [is] a library that replaces the event-driven paradigm with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and most importantly allows the design’s logic to be constructed by a Python program,” Whitequark explains of the project, which is based on Migen but wholly rewritten. “This last point enables hardware designers to take advantage of the richness of the Python language — object oriented programming, function parameters, generators, operator overloading, libraries, etc. — to build well organised, reusable and elegant designs.
“Onwards to simulator and standard library improvements in 0.2 now!”
nMigen v0.1 can be downloaded from the M-Labs GitHub repository now.
FPGAwars Releases Icestudio v0.5.0, adds Generic Blocks, Submodules
Developer Jesús Arroyo Torrens has released version 0.5.0 of Icestudio, the visual block-based editor for FPGA development built on top of the Icestorm project using Apio.
“Icestudio stable v0.5.0 released,” Jesús writes. “Thanks @cavearr for the awesome new features: submodule edition, copy & clone blocks, generic blocks, labels, and updates detection,” the latter prompting the user if a newer release is available than is current running on the system.
The v0.5.0 release brings no additional compatibility for new development boards, though the list of compatible boards is already impressive with popular devices including the Alhambra and its successor, BlackIce, TinyFPGA B2 and BX, iCEBreaker, and UPDuino families.
The latest release can be downloaded now from the FPGAwars GitHub repository.
FOSSi News In Brief
- Andrew Souto releases an HDL checker “because your text editor doesn’t have to be stuck in the 1980s like most EDA dev tools!”
- Symbiotic EDA launches new video series: Getting Started with Formal Verification.
- lowRISC’s Pirmin Vogel on “getting stuff executed” with Ibex on FPGA.
- IEEE Spectrum: “X-Ray Tech Lays Chip Secrets Bare.”
- A teeny-tiny transistor-transistor logic processor: the 1 Square Inch TTL CPU.
- “The Thing:” A home-made FPGA board with Arduino STM32.
- IEEE Micro issues call-for-papers, plans special issue on agile and open-source hardware.
- LLVM receives support for draft RISC-V bit-manipulation extensions.
- SnapEDA interviews KiCad’s Wayne Stambaugh: “Why open hardware needs open software.”
- SourceSort interviews Urban Bruhin of the LibrePCB project.
- Software developer Thanassis Tsiodras has a crack at putting soft-cores on a salvaged FPGA.
- Event: Open Source Design Verification Workshop, 14–15th November, Munich.
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