Google Funds Development of Yosys Spartan 3, Spartan 6 Support
Google has provided funding to Symbiotic EDA to extend the popular Yosys package with Spartan 3 and Spartan 6 support — giving those who had been left out in the cold by Xilinx’ lack of support a free and open source way to continue using the parts.
“This is a prime example of the benefits of FOSSi,” says Free and Open Source Silcon Foundation director Olof Kindgren. “There’s nothing wrong with the old Spartan devices other than the silly reason that Xilinx has no incentive to upgrade the old and buggy Verilog parser which has prevented easy porting of designs to these devices.”
“Spartan 6 should now be supported out of the box (synth_xilinx -family xc6s -ise), with the same support level as Series 7. If anything is not working as expected, it’s a reportable bug,” explains Yosys developer Marcin Kościelnicki of what the funding has actually provided to Yosys users. “ISE output should also be working as expected (use write_edif -pvector bra <file>.edif), and should be usable for all families supported by both ISE and Yosys (ie. Virtex 6, Spartan 6, Series 7, and some limited WIP support for Virtex 5).
“Spartan 3 (and Virtex 2/4) support will happen at some point (it’d be very useful for me personally), and some initial work has been done (the blackbox cells are all there, and multiplier/DSP mapping is supported), but the whole mapping process needs to be changed to support LUT4 Xilinx devices — don’t expect that to happen soon.”
More information is available on the Yosys GitHub issue tracker.
Barcelona Supercomputer Centre (BSC) Opens the European Laboratory for Open Computer Architecture (LOCA)
The Centro Nacional de Supercomputación (Barcelona Supercomputer Centre, BSC) has announced the formal launch of the European Laboratory for Open Computer Architecture (LOCA), a facility which aims to develop open silicon suitable for the ultra-low-power through to the high-performance compute (HPC) markets in Europe.
“LOCA will be a collaborative laboratory that welcomes companies, foundations and academic institutions that share the vision that it is necessary to create open architectures to guarantee transparency, competitiveness, and technological sovereignty,” explains Professor Mateo Valero, director of the BSC. “We are launching it with great conviction, because it is another step in our philosophy of paving the way for the creation of European HPC architectures, as we did in the past with the Montblanc project, creating a clusters based on ARM processors and we are currently doing in the EPI project by developing the general software stack and a RISC-V accelerator in the Arm-based multicore chip.”
“We envision a future that is wide open, incorporating open source software and hardware,” adds Dr. John Davis, LOCA head. “LOCA is a mechanism to extend the success of OSS, like Linux, to the hardware domain. We can no longer rely on Moore´s Law for dramatic improvements in CPU performance. To unlock the potential energy efficiency and performance of future systems, we must use hardware/software co-design, enabled by an open hardware and open software ecosystem. LOCA’s inaugural five-year plan focuses on developing and building key open European-made IP as a basis for future Exascale and beyond systems.”
More information is available on the BSC website.
Wave Computing Closes the MIPS Open Initiative, Less Than a Year After Launch
Wave Computing, which acquired the MIPS business from Imagination Technologies in June 2018, has announced the immediate closure of its MIPS Open initiative — less than a year after opening the ISA.
“Having spent years in the open source technology movement, I can attest to the hunger for community-driven solutions,” claimed Art Swift at the launch of the MIPS Open initiative back in December last year, positioned as a well-established alternative to RISC-V and other open ISA efforts. “However, until now, there has been a lack of open source access to true industry-standard, patent-protected, and silicon-proven RISC architectures.
“The overwhelmingly positive response we have received thus far from customers on our MIPS Open initiative is an indication of the dramatic, positive impact we believe the program will have on the industry. We invite the worldwide community to join us in this exciting journey and look forward to seeing the many MIPS-based innovations that result.”
While the “open” aspect of MIPS Open was questionable — with users being asked to agree to an “open use” licence containing numerous restrictions on how the ISA and related technologies could actually be used — it is now officially closed, with those signed up to the programme receiving an email from Wave Computing’s legal department announcing the closure with immediate effect.
“While current active licenses and previous downloads of MIPS Open Components, and any certifications related thereto, will continue to be honoured,” the company’s brief email to users reads, “Wave recommends its developers, partners and customers restrict further development, as Wave will no longer provide maintenance or support for any of the MIPS Open Components licensed under MIPS Open. In addition, Wave is no longer authorising any third-party certifications as of the Effective Date.”
Wave Computing has not given a reason for the closure of the MIPS Open initiative.
SparkFun Launches RED-V RedBoard, Thing Plus RISC-V Dev Boards
Hobbyist electronic specialist SparkFun is aiming to bring the RISC-V instruction set architecture to a broader audience with the launch of a pair of Arduino-inspired development boards featuring the RISC-V-based SiFive Freedom E310 system-on-chip (SoC): the RED-V family.
“What sets the RED-V RedBoard [and Thing Plus] apart from the rest is the completely open-source approach from hardware to ISA,” SparkFun claims of its latest designs. “That means anyone can make full use the microcontroller without requiring royalties, licenses, or non-disclosure agreements.”
Both the RED-V RedBoard and the RED-V Thing Plus feature the SiFive Freedom E310 SOC, based around a 32-bit RV32IMAC core running at 150MHz. The two differ only in form factor: the RedBoard is based on the popular Arduino Uno layout, including compatibility with Arduino Shield add-on boards; the Thing Plus uses a smaller Feather-inspired gumstick footprint.
The company has both boards available now, with more information — and purchase links — available from its getting started guide.
Antmicro Details sv-tests Open-Source SystemVerilog Test Suite
Antmicro has released additional details of sv-tests, its open-source SystemVerilog Test Suite addition to the SymbiFlow project, following presentations on the tool at ORConf and the CHIPS Alliance workshop in Munich earlier this year — described by the company as “an open source test suite for testing open source, against open source.
“Today different open source tools would usually ship with their own Verilog preprocessor and parser, based on their needs and use cases, and history,” the company explains. “The result is that SystemVerilog support is at best partial, and at worst — non-existent, which makes those tools barely usable to ASIC designers. There is no common infrastructure, and no common benchmark to compare against.
“The purpose of the SystemVerilog Test Suite project (sv-tests for short) is to pinpoint all the supported and missing SystemVerilog features in various Verilog/SystemVerilog tools,” the company explains. “That is achieved by running a large number of tests over each of the tools examined.
“The outcome of this test suite is a regularly updated table showing the results each of the tools got for each tag. Clicking on any cell of the report table shows a window with some detailed information about the selected test case (including its source code) and its execution on the selected tool. All of the results are summarised at the bottom of the table, where we can see the total tests passed as well as the total number of tags for which all of the tests passed.”
More information on the tool, which is already being used to improve the software on test, can be found on the Antmicro website.
Josh Bassett Writes Open SDRAM Controller IP, Documents the Process
Developer Josh Bassett has published a guide to using synchronous dynamic RAM (SDRAM) in FPGA projects, after finding that he could “barely understand” how the majority of open-source SDRAM controller IP available actually worked.
“There are many open-source and proprietary SDRAM controller IPs available, and after having written one myself, I can definitely see the appeal in using something off-the-shelf,” Josh explains. “But where is the fun in that?
“The IPs I did manage to try either didn’t work properly, had missing bits of functionality, or had interfaces that were too complex to be suitable. That was when I decided to roll up my sleeves and write my own memory controller. In retrospect, it wasn’t a decision to be taken lightly — it took many iterations before I finally had something I was happy with.”
The result is a custom-written SDRAM controller coupled with a detailed write-up of how and why it operates in the way it does. The full write-up is available on Josh’s website, while the controller IP is available on GitHub under the MIT licence.
The OpenRAM Project Receives $75,000 Gift from Google to Fund Development
The OpenRAM project, maintained by the VLSI Design & Automation Group of the University of California at Santa Cruz and which presented at the Latch-Up conference earlier this year, has announced the receipt of a $75,000 gift from Google to fund further development.
“OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design,” the project’s maintainers explain. “OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.”
“Very grateful to announce a $75k gift from Google (thanks to @mithro! [Tim Ansell]) to support our project,” the team announced via Twitter. “Google continues to support open-source projects and we are glad to be a part of this!”
More information the project is available via its GitHub Pages site.
ETH Zürich Researchers Unveil Energy-Efficiency Ara RISC-V Vector Processor
A team of researchers at ETH Zürich have published a paper detailing Ara, a scalable and energy-efficient RISC-V vector processor implemented on a 22nm FD-SOI process and clocking upwards of 1GHz.
“We present Ara, a 64-bit vector processor based on the version 0.5 draft of RISC-V’s vector extension, implemented in GlobalFoundries 22FDX fully depleted silicon-on-insulator (FD-SOI) technology,” the researchers explain in the paper’s abstract. “Ara’s microarchitecture is scalable, as it is composed of a set of identical lanes, each containing part of the processor’s vector register file and functional units.
“[Ara] achieves up to 97% floating-point unit (FPU) utilization when running a 256 x 256 double-precision matrix multiplication on 16 lanes. Ara runs at more than 1 GHz in the typical corner (TT/0.80 V/25 $°C), achieving a performance up to 33 DP-GFLOPS. In terms of energy efficiency, Ara achieves up to 41 DP-GFLOPS W⁻¹ under the same conditions, which is slightly superior to similar vector processors found in the literature.
“An analysis on several vectorisable linear algebra computation kernels for a range of different matrix and vector sizes gives insight into performance limitations and bottlenecks for vector processors and outlines directions to maintain high energy efficiency even for small matrix sizes where the vector architecture achieves suboptimal utilisation of the available FPUs.”
The full paper, authored by Matheus Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, and Luca Benini, is available under early access via the journal IEEE Transactions on Very Large Scale Integration Systems. Luca Benini, meanwhile, has indicated through Twitter that Ara will be “open sourced very soon.”
Craig Bishop Unveils the Gameslab FPGA-Based Handheld Games Console
Developer Craig Bishop has published a series of posts unveiling the Gameslab, an FPGA-based handheld games console which began life as a conference badge project.
“f you went to Hackaday Supercon 2019, you might have seen someone wandering around with a badge that was way too heavy looking. That was me,” Craig explains. “And that badge was a Gameslab, my FPGA-powered handheld game console. As the blog posts from years ago prove, I’ve been thinking about building Gameslab for a long time, and over the last few months, I have finally done it.
“The Gameslab is a custom-designed handheld game console based on a Xilinx Zynq FPGA-ARM Cortex A9 combo SoC. The FPGA fabric means that games and apps can bring their own unique hardware to load into the fabric. For example, a 2D side-scrolling shooter can load hardware to accelerate drawing and animating sprites on the screen. Or, a Gameboy emulator could load a Gameboy’s CPU and peripherals into the FPGA fabric to ‘become’ a Gameboy rather than emulating it in software.”
The Gameslab is designed around an open-source ethos: the device itself was created in KiCad — “even the painful, high-speed DDR3 interface,” Craig explains — while an on-board microcontroller runs embedded Rust-based firmware, the Zynq FPGA runs a ported Das U-Boot bootloader loading a custom-compiled mainline Linux kernel and a Debian-derived operating system dubbed SlabOS.
Craig has promised to write additional posts going into more detail about the development and use of the Gameslab: at the time of writing, he had published a project overview, a look at some failures, and a detailed look at the console’s housing.
Zoltan Pekic Releases a VHDL Implementation of Two Classic Calculators
Software engineer Zoltan Pekic has published a VHDL implementation of two classic electronic calculators from the 1980s: The Texas Instruments Datamath and the Sinclair Scientific.
“Not one, but two vintage desktop calculators rolled into a single FPGA,” Zoltan writes of his project. “The ‘chip’ is hosted within glue logic that provides interface to the Mercury baseboard hardware (switches, buttons, 4 digit LED, VGA). The keyboard is hex PMOD, the keys change meaning if in TI or Sinclair mode. All of this is (somewhat) documented here or in the source code.
“The core of the implementation is 256 deep * 52 bit wide microcode routine. In a single clock cycle, a single 4-bit digit is processed, and to execute a single TMS0800 instruction, usually 12+ cycles are needed. Both modes are operational, but with some bugs. Time permitting I may continue fixing them and improving. I hope somebody finds this project interesting, it was tons of fun and learning, and truly fascinating journey into retro-computing!”
Full details are available on Zoltan’s Hackaday project page.
Enjoy Digital Announces Open-Source USB 3.0 PIPE Support on ECP5 SERDES
Enjoy Digital has released an open-source implementation of USB 3.0 on Lattice Semiconductor’s SERDES-enabled ECP5 platform — using a fully open-source toolchain.
“Our expert just also got a first USB3.0 link up with ECP5 SERDES,” the company announced via Twitter, “using full open-source code and toolchain!” The expert in question: a small child, pictured on the company’s Twitter account enjoying an explore of the development system’s keyboard.
The announcement came mere days after the same unnamed tooth-cutting developer is claimed to have added Xilinx 7-series support to the company’s USB3 PIPE, originally launched in an attempt to avoid the need for external high-speed transceivers in order to add USB 3.0 support to a project — and, potentially, to expand the PIPE interface to support additional protocols in the future, including PCI Express, SATA, and DisplayPort.
The USB3 PIPE project can be found on Enjoy Digital’s GitHub repository under the BSD 2-Clause licence.
FOSSi News In Brief
- Chips4Makers: “SnowWhiteIII test chips have arrived.” (More information in the ORConf presentation.)
- Think Silicon puts RISC-V to work as a 3D-capable general-purpose GPU.
- The OpenROAD Project releases push-button DRC-clean RTL-to-GDS v1.0 expectations document.
- lowRISC: “Get Started with OpenTitan.”
- Gisselquist Technology: “Formally Verifying a General Purpose Ultra-Micro Controller.”
- Vision FPGA SoM: An FPGA-based System-on-Module with integrated vision, audio, and motion-sensing.
- FentISS: “Lift-Off: De-RISC to Create First RISC-V Fully-European Platform for Space.”
- SiFive revisits the maker space with SiFive Learn Initiative, FE310-based educational development board.
- Sean Cross: “Want Python in your USB port? Try the beta of Adafruit CircuitPython for Fomu!”
- Linux 5.5 brings numerous RISC-V features and improvements.
- KiCad open-source EDA project joins The Linux Foundation.
- RISC-V Foundation announces “Student of the Year,” “Educator of the Year” awards.
- NedoPC-5, a RISC-V-based DIY personal computer.
- RISC-V Foundation moves to Switzerland over US embargo concerns.
- Event: Second Workshop on Open-Source Design Automation, Grenoble, France, March 13th 2020.
- Event: RISC-V Summit 2019, San Jose, California, December 10–12th 2019 (and here are Antmicro’s plans.)
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