El Correo Libre Issue 24

Published in

LibreCores

12 min readFeb 11, 2020

Announcing Latch-Up Cambridge, Massachusetts

Following up on the fantastic event we had in Portland, Oregon last year we have set our sights on the US East coast this year. We hope to make this Latch-Up slightly bigger and better this year, but in all other regards it will be a familiar setup in the spirit of previous Latch-Up and our long-running ORConf

Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a wide range of topics; open source IP blocks and SoCs, open source simulators, compilers, synthesis and physical implementation tools for both FPGA and ASIC.

Latch-Up aims to bring together the North American open source digital design community for an event in the mould of ORConf — the FOSSi Foundation’s annual European community conference. Like ORConf, Latch-Up will be will be free to attend and consist of a relaxed format of presentations and discussions throughout a weekend, with plenty of time for networking. A dinner on the Saturday evening will be arranged and all attendees are invited to attend.

These events go to the FOSSi Foundations’ goal of lowering barriers of entry to the digital design field, whilst encouraging the open source development model and promoting open collaboration.

We recognise the keen interest in this area in the Americas and this year are putting effort into organizing an event which will encourage wider awareness amongst enthusiasts of the projects that we’ve been hearing about at ORConf since 2012.

The event will be free of charge but attendees are required to register. As with all events organized by FOSSi Foundation, participants are expected to follow the FOSSi Foundation code of conduct.

Presentation submissions are now open!

Submit your proposals through the registration form.

We invite anyone who is involved in any aspect of open source digital design and embedded systems engineering to join us and choose between anything from a lightning talk up to a 30 minute presentation on a relevant topic.

All presentations at Latch-Up will be recorded (with your permission) and posted on the FOSSi Foundation’s YouTube channel under a CC-BY license after the event.

Latch-Up will be free of charge to attend but we aim to raise money to provide catering throughout the event, and possibly cover the cost of the conference dinner on the Saturday night. Events like Latch-Up are a great way to get your brand in front of a passionate audience of engineers. Please get in touch if you’d like to view our sponsorship packages and help make Latch-Up a success.

We also need folks on the ground to lend a hand — so if you have any expertise in helping to run or staff such events, your help would be greatly appreciated, so please do get in touch to let us know you’d like to help out.

Whether you want to assist or simply attend, go to the website, register and let’s catch up at Latch-Up!

-Olof Kindgren, Director, Free and Open Source Silicon Foundation

Microwatt OpenPOWER Core is Now GHDL Compatible via Yosys, Nextpnr

IBM developer Anton Blanchard has submitted a patch for the Microwatt soft core OpenPOWER implementation, bringing compatibility with the GHDL via the Yosys and nextpnr open-source toolchain.

“A first pass at GHDL synthesis using Yosys and nextpnr,” Anton writes of the commit which added support. “It runs ‘hello world’ or MicroPython if the FPGA has enough block RAM (eg ECP5 85F). The ‘hello world’ testcase also loops UART RX to TX in software (ie not a hardware loopback).

“It uses Docker images, so no software needs to be installed. We need to add PLL support. Right now Microwatt runs at whatever the external clock frequency is and the baud rate gets scaled by how far off 50MHz it is. This means on the ecp5-evn with a 12 MHz clock rate the baud rate is a quite strange 27650 (115200 * 50 / 12). On my OrangeCrab with a 50MHz clock the UART is 115200.”

While Microwatt in GHDL is functional, Anton warns that it uses “a large amount of resources, way more than it should.”

The commit is available on Anton’s GitHub repository, while an image of the ppc64le OpenPOWER ISA running on an OrangeCrab FPGA board can be found on his Twitter stream.

Gaurav Singh Releases SPI MIPI DSI Bridge for LCD/TFT Panel Control

Engineer Guarav Singh has documented a project to build an open-source SPI to MIPI DSI bridge — with a view to using it as a means of controlling low-cost colour displays salvaged from Apple iPod Nano devices.

“As display technology is advancing, high resolution LCD/TFT LCD panel are becoming more common,” Guarav writes of his project. “With higher resolution comes nicer picture quality, rich content with higher bandwidth requirement to transfer that content from the display controller to the display it self. Gone those days of 8-bit parallel bus, now MIPI [Display Serial Interface] is becoming more and more common with nice display.

“Yes one can still buy parallel or LVDS interface display. But as one try to move towards nicer quality display MIPI is becoming dominant. Basic MIPI DPHY can achieve 1Gps per-lane with MIPI DPHY V2.5 you can go up to 6Gbps Max total bandwidth.”

Rather than use a proprietary MIPI DSI block, Guarav created his own — including reverse-engineering the iPod display itself through some very fine-pitch soldering — and has released the FPGA source, hardware design, and a Qt5 application for driving the display under the GNU General Public Licence.

More information is available on Guarav’s blog, while the code can be found on his GitHub repository.

Winston Lowe Recreates the COSMAC Elf Microcomputer in SpinalHDL

Originally brought to life through a series of articles in Popular Electronics in the late 1970s, the COSMAC Elf microcomputer — built around the RCA 1802 microprocessor, constructed using the complementary symmetry monolithic array computer architecture that gave it its name — lives again, in SpinalHDL form, thanks to Winston Lowe.

“The goal of this project is to end up with a cycle-accurate [RCA] 1802 processor that can be used in FPGA designs easily,” Winston explains of the effort. “When I start the project I was new to SpinalHDL but I had attempted in the past to write the same processor in VHDL. However, language complexity and the sheer amount of code and time needed to write and debug that project ended the work on it.”

Switching from VHDL to SpinalHDL appears to have been the breakthrough required: the project is now in functional form, and late last month received an upgrade to include the CDP1861 video display controller — enough to offer a display resolution as high as 64x128.

The full project write-up is available on Hackaday.io; Winston’s source code, meanwhile, can be found on GitHub under the GNU General Public Licence 3.

Rust Meets RISC-V, SpinalHDL, and SymbiFlow on the Hackaday Supercon Badge

“What do Rust, RISC-V, and SpinalHDL all have in common,” Craig J. Bishop asks in introduction to his latest project. “They can all run on the Hackaday Supercon 2019 badge!”

Craig’s post goes on to explain how to install and use SpinHDL, SymbiFlow, Yosys, nextpnr, and Project Trellis to place a simple “blinky” LED animation bitstream onto the FPGA-powered handheld badge device given out at the Hackaday Supercon late last year — then to expand it with a counter.

Things get really interesting, however, when Craig shifts his focus to VexRiscv, then to set up a Rust development environment for the VexRiscv core — eventually ended up with Rust on RISC-V on SymbiFlow on the SuperCon 2019 badge.

Craig’s full write-up is available on his website, while the source code can be found on his GitHub repository.

Jared Stanbrough Publishes Proof-of-Concept IceFM SpinalHDL FM Transmitter

“I’ve just published an experiment with SpinalHDL,” developer Jared Stanbrough writes: “a simple PLL driven FM transmitter for the Lattice iCEstick. Transmits a carrier only, with a frequency range between ~12Mhz and ~265Mhz. Use responsibly!”

The IceFM transmitter, which is in theory compatible with any Lattice FPGA with phase-locked loops (PLLs), works by bridging two different technologies: the Icestorm icepll package, which generates Verilog modules to instantiate the PLL, and SpinalHDL’s BlackBox component for importing arbitrary Verilog into a project.

Those with the prerequisites installed — sbt, Yosys, nextpnr-ice40, and Icepack — can find the source, plus example Verilog files targeting transmission on 109.5MHz, on Jared’s GitHub repository — but should check their local laws for the legality of unlicensed transmission.

Intel Joins CHIPS Alliance, Donates Advanced Interface Bus Standard

Semiconductor giant Intel has announced its membership of the CHIPS Alliance, and it has brought with it the gift of the Advanced Interface Bus (AIB).

“We couldn’t be more happy to welcome Intel to CHIPS Alliance.” says Dr. Zvonimir Bandić, chair of CHIPS Alliance and senior director of next-generation platforms architecture at Western Digital. “Intel’s selection of CHIPS Alliance for the AIB specifications affirms the leading role that the organisation impacts for open source hardware and software development tools. We look forward to faster adoption of AIB as an open source chiplet interface.”

AIB is presented as an open-source, royalty-free PHY-level standard for the connection of multiple semiconductor dice in a single package — the so-called “chiplet” design which is becoming increasingly common in high-performance many-core parts, in particular for the mixing of different manufacturing nodes on a single chip.

The AIB documentation has already been added to the CHIPS Alliance GitHub repository, under the permissive Apache Licence 2.0.

IBM Releases Open-Source OpenCAPI Acceleleration Framework, CAPI FlashGT IP

IBM has open-sourced two more technologies under its OpenPOWER umbrella, following the release of the POWER ISA and supporting technologies last year: CAPI FlashGT and the OpenCAPI Acceleration Framework.

“With exploding amounts of data involved in modern workloads, we believe that open source hardware and an innovative ecosystem is key for the industry,” explains IBM’s Mendy Furmanek, president of the OpenPOWER Foundation. “So to lead the industry forward in that direction, we’ve continued to make additional contributions to the open source community.”

Announced during the OpenPOWER Summit Europe late last year, CAPI FlashGT is the last brick in the FlashGT wall to be open-sourced. Designed to reduce latency by moving system calls from the software stack to hardware, CAPI FlashGT is claimed to offer up to a sixfold performance improvement for random read operations per code.

The OpenCAPI Acceleration Framework, OC-Accel, is an integrated development environment designed specifically for the creation of FPGA-based accelerators. “Put simply,” Mendy explains, “it enables virtual memory sharing among processors and OpenCAPI devices. Our open-sourcing of the OC-Accel bridge makes everything needed for an OpenCAPI device available today.”

More information, including links to both projects’ source, can be found on the OpenPOWER Foundation website.

Anatoly Trosinenko Releases MemTest86+ RISC-V Port

Anatoly Trosinenko has released a proof-of-concept port of the popular MemTest86+ memory testing utility for the RV64IM RISC-V ISA — and offers it up in the hopes it will be “interesting to someone else.”

“As an attempt to make my development board with DDR2 SO-DIMM slot self-contained (not relying on other x86 computer for memory module testing — DDR2 is quite rare nowadays) and just out of curiosity, I have implemented a Proof-of-Concept port of MemTest86+ v5.1 to RV64IM ISA,” Anatoly writes.

“This port can already run on my build of RocketChip but is still early WIP, so use at your own risk (and probably do not use at all on real hardware, unless you absolutely know what you are doing). One of known issues is that reserved areas of RAM from FDT are not yet handled at all.”

The port is designed to better support multiple architectures in the future by moving as much platform-specific code to a dedicated arch/ directory as possible, but Anatoly warns it has not yet been tested for safety and reliability and that the port has broken symmetric multiprocessing (SMP) capabilities — along with the tool’s ability to measure cache memory and RAM speed.

The code is available now on Anatoly’s GitHub repository.

Drew Fustini Pens an Intro to RISC-V for Hackspace Magazine

The core concepts behind free and open source silicon in general and the RISC-V ISA specifically have been brought to a wider audience courtesy of OSH Park’s Drew Fustini, who wrote an introduction to the topic for Raspberry Pi Press’ Hackspace Magazine’s latest issue.

“When we think about what open source hardware means, we usually think about the board design being freely available.” Drew writes in the piece. “But what about the processor? Is there a way to make hardware that is truly open source? This month’s column is dedicated to an exciting — and surprisingly political — development in chip design.

“Chances are that both your laptop and the datacentre streaming your favourite movie are using an ISA owned by Intel or AMD. The processor in your smartphone is almost certainly using a proprietary ISA licensed from ARM. This is dangerous: proprietary standards can be over-priced, prevent innovation or even disappear altogether when companies change strategy.”

The column is available now in Hackspace Magazine Issue 27, which can be downloaded free of charge under a Creative Commons licence.

Cobham Gaisler Verifies NOEL-V, its First RISC-V Processor Core

Following on from the announcement late last year that it was to produce and release an open source RISC-V processor core, NOEL-V, to join its traditional SPARC designs, the company has now announced its formal verification.

The verified NOEL-V is a synthesisable 64-bit RISC-V processor, written in VHDL, with a seven-stage dual-issue in-order pipeline offering a claimed performance of up to 4.69 CoreMarks per megahertz. As with the company’s earlier design, its primary focus is high-reliability use — including in spacecraft.

“For nearly 20 years, Cobham’s LEON processors, which are based on the open SPARC ISA, have been used in RadHard and High Reliability microelectronics solutions in hundreds of spacecraft due to their rich feature set and dependability,” said Cobham Gaisler’s director of engineering Jan Andersson at the launch. “We intend to release products based on the RISC-V ISA in parallel with the further development of our LEON SPARC processor based products, including the LEON5 processor core.”

“Because of its open-source model, RISC-V is a game-changing technology for hardware that spans across various embedded applications including space and mission-critical,” claims Aldec’s Louie De Luna, who provided Cobham Gaisler with its the Riviera-PRO tool for verification. “We’re excited to help and work with Cobham Gaisler, and we look forward to solving new verification challenges for the future generations of NOEL-V.”

More information on the NOEL-V processor is available on the company’s website.