El Correo Libre Issue 27

Published in

LibreCores

15 min readMay 12, 2020

Google Summer of Code Class of 2020

The FOSSi Foundation is happy to announce that we have been granted eight slots by Google to support projects and students for another year’s edition of Google Summer of Code. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects.

These projects are our “GSoC Class of 2020”. The students will introduce themselves over the coming days to the various projects, please give them a warm welcome!

Integrating ao486 with BYOC Framework (Manan Gupta)
Mentored by Kunal Gulati and Jonathan Balkind

This project involves a heterogeneous-ISA system based on a BYOC (Bring Your Own Core) framework. This provides a cache coherent, manycore research framework meant to support a variety of ISAs. The ao486 core having a x86 ISA, provides support for legacy code and is one of the few open source CISC ISAs. The initial approach to integration involved connecting BYOC through the Avalon interface. In this project, work is done with the bare interface of ao486 to interface it with BYOC to maintain cache coherency across all cores.

Adding Deployment-Phase Tracing Features (using Timeprints) To Open SoC Debug Platform (Rehab Massoud)
Mentored by Philipp Wagner and Stefan Wallentowitz

This project aims at adding deployment-phase tracing features, to the Open SoC Debug platform existing tracing features. OSD is still following the traditional tracing methodologies, which are mainly concerned with instructions executed, cache miss/hit rates monitoring, registers monitoring…etc. While these methods are useful for debugging and tracing at development time, they produce huge amounts of data which makes them very un-efficient to use during deployment.

Recently, a new methodology for deployment-time efficient tracing, based on Timeprints, was proposed. Timeprints are periodic summaries of the temporal behavior of the traced signals. They are lightweight logs, triggered by executions, and can only produce useful information with off-line “Reconstruction”.

In this Project, I want to make deployment-time tracing and checking, enabled by Timeprints, part of the OSD platform. This includes work on two fronts: 1) Developing deployment-phase trace specifications within the OSD specifications, and 2) Developing standard modules to support this in OSD. In the third phase, a working implementation with the newly released RISC-V trace specifications is expected.

Integration of WARP-V with OpenPiton (Shivam Potdar)
Mentored by Ákos Hadnagy, Jonathan Balkind and Steve Hoover

WARP-V is an open-source and highly flexible and configurable CPU core with customisable ISA and pipelines written in the emerging “Transaction-Level” modelling. OpenPiton is an open-source, general-purpose, multi-threaded manycore framework for heterogeneous architecture research.

This project aims to evolve WARP-V further by adding necessary support for memory, microarchitecture extensions etc., and make it RISC-V Linux compatible and then integrate it with the OpenPiton-derived Bring Your Own Core (BYOC) Framework. This would open the doors for the first Linux-capable processor based on TL-Verilog and easy scaling to multicore heterogeneous implementation with OpenPiton.

Improving Logic Visualization with an Interactive Platform (Cole Johnson)
Mentored by Aliaksei Chapyzhenka and Olof Kindgren

Digital logic designs can become very complex. Like many fields of engineering, visual analysis and debugging tools can greatly aid developers, reverse-engineers, and teachers. Existing methods to render digital logic designs have numerous flaws unfortunately.

My project aims to create an entirely new netlist visualization tool. This new tool will feature multiple ways of displaying circuit designs without overwhelming the user. It will also feature close integration with other tools in the logic designer’s arsenal, giving the user visual design information directly beside signal traces and source code.

Automating Hardware and Bitstream Verification for PRGA with cocotb (Ansh Puvvada)
Mentored by Ang Li (primary), Jonathan Balkind and Stefan Wallentowitz

The goal of the project is to automate and augment the verification of the custom FPGA and the bitstream with Cocotb, an open-source framework for verifying VHDL/ Verilog RTL using python. At the end of the project, users will get to generate a bitstream file and also know whether it is correct or not automatically.

Implementing Hypervisor Extensions for Ariane Core (Muhammad Usama Javed)
Mentored by Florian Zaruba, Nils Wistoff and Jonathan Balkind

RISC-V is an open source ISA, and supports 32-bit, 64-bit, and 128-bit implementations. It is designed to be extendable in future to cater for different application needs. Both privileged and non-privileged instructions are included in RISC-V ISA. Recently, hypervisor extensions were released. These extensions are expected not to change much, and to be ratified in near future.

The proposed extensions have two new modes titled hypervisor-extended supervisor mode (HS), virtual S-mode (VS-mode), and virtual U-mode (VU-mode).. Secondly, Ariane is a 6-stage, single issue, in-order CPU, and is an implementation of 64-bit RISC-V ISA being developed at ETH Zurich. This project aims to add proposed extensions to Ariane core.

Enhancement in Warp-V and Optimization (Vineet Jain)
Mentored by Steve Hoover and Ákos Hadnagy

The WARP-V RISC-V core generator was developed in 2018, it is the most-configurable, most-adaptable open-source RISC-V CPU core generator, taking advantage of advanced digital design features of TL-Verilog. Till now WARP-V has support for RV32I base instruction set architecture and is formally verified using Risc-V formal.

My proposal is to implement RV32F(Single Precision Floating-point) Unit extensions to the Warp-V core by using a “hard float by Berkeley” library written in chisel, which also supports IEEE 754 single-precision floating-point unit. My proposal is also to introduce Virtual Memory support(TLB) in Warp-V and to complete the implementation of Bit-Manipulation Instructions.

Integrating OpenPiton with Nyuzi (Gaurav Jain)
Mentored by Jonathan Balkind and Jeff Bush

In this project, we propose to integrate the Nyuzi core with the OpenPiton platform. To be able to model and conduct research on heterogeneous systems, it is important that the community has access to platforms that allow them to run applications that are not restricted by the computational-limitations of the CPU-cores, but also allows them to run more recent workloads such as those belonging to the domain of machine learning and deep learning.

We believe that the integration of the OpenPiton core with Nyuzi would provide a first of its kind, completely synthesizable, open-source, multi-core, heterogeneous platform, that would provide simulation, emulation, and implementation capabilities to the researchers.

-Philipp Wagner, Director, FOSSi Foundation

SERV Video Details “The World’s Smallest RISC-V CPU”

FOSSi Foundation director Olof Kindgren has published a video walking through the architecture and features of SERV, claimed to be the smallest RISC-V implementation in the world.

SERV — the Serial RISC-V CPU — has already been ported to a range of development boards including the TinyFPGA BX, ICEBreaker, Digilent Arty A7 35T, Saanlima Pipistrello, abd Alhambra II, taking up as few resources as possible.

In the eight-minute video which was first presented at the Munich RISC-V Meetup in April, the region’s second RISC-V meet but first to take place entirely virtually, Olof walks through the concept of bit-serial architectures, a history of SERV’s development, and a look at both what the core is good for and where it is currently being used.

The video is live now on Diode Zone, while SERV itself has been published on GitHub under the permissive ISC Licence.

PULP Researchers Detail Prevention Techniques for Covert Channel Attacks

Researchers working on the free and open source silicon PULP Platform project have released a paper detailing a series of microarchitectural covert channel attacks, of the type which have plagued mainstream silicon in recent years, and how they can be prevented in the Ariane 64-bit RISC-V core.

“Covert channels enable information leakage across security boundaries of the operating system,” the researchers explain in their paper’s abstract. “Microarchitectural covert channels exploit changes in execution timing resulting from competing access to limited hardware resources.

“We use the recent experimental support for time protection, aimed at preventing covert channels, in the seL4 microkernel and evaluate the efficacy of the mechanisms against five known channels on Ariane, an open-source 64-bit application-class RISC-V core.

“We confirm that without hardware support, these defences are expensive and incomplete. We show that the addition of a single-instruction extension to the RISC-V ISA, that flushes microarchitectural state, can enable the OS to close all five evaluated covert channels with low increase in context switch costs and negligible hardware overhead. We conclude that such a mechanism is essential for security.”

The full paper is available on arXiv.org now, under open-access terms.

“Starbleed” Vulnerability Found in Commercial FPGA Hardware

Researchers from the Horst Görtz Institute for IT Security at Ruhr-Universität Bochum and the Max Planck Institute for Security and Privacy have detailed a vulnerability in commercial FPGAs, dubbed Starbleed, which allows for supposedly-protected bitstreams to be decrypted and modified by an attacker.

The vulnerability has been confirmed as affecting Xilinx Spartan, Artix, Kintex, and Virtex 7-series FPGA parts as well as previous-generation Virtex-6 chips. “We informed Xilinx about this vulnerability and subsequently worked closely together during the vulnerability disclosure process,” says Dr. Amir Moradi of his team’s work with the company. “Furthermore, it appears highly unlikely that this vulnerability will occur in the manufacturer’s latest series.”

“It’s an excellent example of why companies that are conscious about security should demand that the FPGA vendors document their FPGA binary format,” says FOSSi Foundation director Olof Kindgren of the vulnerability. “That would allow the users to verify the functionality much easier.

“Thankfully we are finally seeing some FPGA vendors starting to realize this, and I’m fully convinced these are the ones that will grab market-share in security- and safety-sensitive areas such as defence, automotive, aerospace and data centres and hopefully others will follow. I’m pretty convinced that anyone remotely concerned with safety in software would stay away from a CPU where the format of the executables are a guarded secret and can’t be inspected, and you just have to trust the CPU vendor that it hasn’t been tampered with.”

The team’s paper is available to download under open access terms on the Usenix website, while Xilinx has published a design advisory confirming the vulnerability but claiming it is “similar to well-known, and proven, DPA [Differential Power Analysis] attacks against these devices and therefore [does] not weaken their security posture.”

BSC Announces Safety Features Unlocking Full SELENE RISC-V Performance

The Barcelona Supercomputer Centre (BSC) has announced the development of safety features allowing for full performance from the RISC-V cores used in the European Union’s SELENE self-monitoring safety-critical open-computing initiative.

“Throughout years of research, BSC has developed the know-how to reconcile high-performance and safety demands in the safety-critical domain,” says Jaume Abella, BSC Principal Investigator for SELENE and senior researcher of the Computer Architecture-Operating System research department at the Centre. “SELENE offers a unique opportunity to materialise this know-how in an industrial setup.”

The SELENE project aims to create a fully-open hardware and software platform, built around heterogeneous RISC-V cores with integrated safety features, for a range of safety-critical applications including autonomous vehicles, trains, satellites, and even a RISC-V-powered deep-space station — the latter in partnership with Airbus Defence and Space.

The BSC’s contribution to the project is designed to close the performance gap between high-performance and safety-critical systems by offering diverse redundancy and a timing verification process for multicore use.

More information on SELENE is available on the official website.

Antmicro Announces Verible, FuseSoC Integration

Antmicro has announced that it has integrated Verible, an open-source SystemVerilog parser, linter, and formatter, into FuseSoC, as a means of bringing the technology to a wider audience.

“Although new ASIC design methodologies and tools such as Chisel are on the rise, most ASIC projects still use SystemVerilog, the support of which in open source tools has traditionally lagged behind,” the company writes. “Antmicro, Google and the CHIPS Alliance, which we are members of, have been working together with the lowRISC project to address this issue by implementing relevant tools and useful integrations in the open source domain. One large milestone on this route is Verible, an open source Flex/YACC SystemVerilog parser, linter and formatter recently open sourced by our partner and customer, Google.

“Among other developments in that space, Antmicro has been helping to make Verible support some SystemVerilog features required for working with practical use cases, such as lowRISC’s ibex, a 32-bit RISC-V core used in the open source security project, OpenTitan. But to generate adoption, ease of use is just as important as features, which is why Verible was recently exposed to a wider audience by integrating it with FuseSoC.

“One of the main advantages of an open source linter/formatter is how easy it is to integrate it with existing workflows of open source projects. As it happens, many open source FPGA/ASIC projects, including OpenTitan, are managed with FuseSoC, an open source tooling and IP package manager (from our fellow FOSSi veteran Olof Kindgren) which we also use and support. Thanks to the integration of Verible with FuseSoC, linting and formatting automation becomes much easier.”

Antmicro’s full write-up, including a hands-on demonstration, can be found on the company website.

Gaurav Singh’s Breakout Board Expands the Avnet MicroZed FPGA SOM

Engineer Guarav Singh has designed his own breakout board for the fine-pitch expansion connectors on the Avnet MicroZed Zynq-based FPGA system-on-module (SOM), after finding the official board design lacking.

“[The] Avnet MicroZed Board has two 100-pin fine pitch connectors for expansion, which is impractical for prototyping,” Guarav explains. “So I decided to make my own breakout board.

“Finding [the official] Avent MicroZed GPIO breakout was little hard and [the] official board has same VCCIO regulator for all banks, and Avnet’s board also does not have differential LVDS layout. So I made this Open source Board, with three separate switching regulator for each bank VCCIO on 4 Layer Gold finish board with most of microZed pins broken out in LVDS pair.

“The PCB is 4 Layer impedance control for 100R LVDS pair. Board has 3 solder jumpers per regulator to change bank voltage of each bank separately.”

Guarav is selling the boards through CircuitValley.com at €39.99 fully assembled, and has published the Gerbers and schematic on GitHub under the Creative Commons Attribution 4.0 International Licence.

Matthew Venn’s iCE40 Board Brings FPGA Goodness to the Raspberry Pi

Developer Matthew Venn has designed an add-on for the Raspberry Pi family of low-cost single-board computers which adds an Icestorm-compatible FPGA to the SBC’s general-purpose input/output (GPIO) header.

Brought to our attention by OSH Park’s Drew Fustini, the board — Matthew’s first PCB design to feature an FPGA — is based around the Icestorm-compatible iCE40-HX4K-TQ144 FPGA with an otional 16MB of flash memory for configuration bitstreams.

The design includes six PMOD expansion headers, two buttons, two LEDs, and a header compatible with the Raspberry Pi’s GPIO pins — including those on the ultra-low-cost Raspberry Pi Zero family.

Matthew’s initial production run of the board used OSH Park’s After Dark service, which features a black substrate and a clear solder mask for an eye-catching black-and-gold finish to the board.

More details are available on the OSH Park website, while Matthew’s schematics, Gerbers, and source code can be found on GitHub.

NEO430 Offers a “Really Tiny” MSP430-Native Microprocessor System in VHDL

Stephan Nolting has published a new MSP430-based soft-core, the NEO430, with which he aims to address the lack of open-source cores between the tiny 8-bit and bigger 32-bit families.

“There is a pretty gap in the landscape of open-source soft-core processors between the tiny 8-bit processors and the chunky 32-bit ones,” Stephan explains of the NEO430 project, brought to our attention by Hackaday. “So I decided to fill this gap with a MSP430-native 16-bit processor.

“The NEO430 is a TI MSP430-native tiny microcontroller-like processor system. The system is highly configurable and provides of standard IO and peripheral components. If a certain module is not required at all it can be disabled and thus will not be synthesised.”

The project is designed to be as cross-platform as possible: Stephan has included Makefiles for Linux, Windows Subsystem for Linux (WSL), and PowerShell, and driver libraries for all peripherals — plus a series of example programs to get users started. The design also boasts full compatibility with the original MSP430 instruction et architecture, though has its own processor modules.

More information is available on the project’s Hackaday.io page, while the source code is available on GitHub under the permissive BSD 3-Clause licence.

Sylvain Lefebvre Creates Wolfenstein 3D, Doom “Chips” on an FPGA

Id Software’s Doom, the saying goes, will run on anything — but Sylvain Lefebvre has taken the concept a step further, creating a soft-core processor which implements the game’s rendering algorithms directly.

“Wolfenstein 3D render loop in pure hardware,” Sylvain wrote of the design’s predecessor, which implemented Doom’s precursor Wolfenstein 3D. “No CPU, no instruction pointer, no opcodes, only wires and flip-flops. Here [it] runs on a Mojo V3 board (Xilinx Spartan 6) + SDRAM.

“Implemented from scratch using my language, from the SDRAM double-framebuffer to the Wolf3D DDA algorithm (and this is the original one; fixed point, DDA loop with only adds and shifts, tangent table!). 320x200, 256 18-bits colors palette and VGA output — old school!”

Doom, logically, followed. “The DooM-chip! It will run E1M1 till the end of times (or till power runs out, whichever comes first),” Sylvain writes. “Algorithm is burned into wires, LUTs and flip-flops on an FPGA: no CPU, no opcodes, no instruction counter. Running on Altera CycloneV + SDRAM.

“Everything is described in a language I am working on: SDRAM controller, divider, BSP traversal, texture unit, etc.
Main renderer (w/o data) is 666 lines of code (!) A great test case, made quite a few improvements, fixed some issues, learned a lot on CycloneV + Quartus.”

Sylvain’s work, which is based on information gleaned from id Software’s original source code and books on the Wolfenstein 3D and Doom game engines published by Fabien Sanglard, can be found on his Twitter profile; Sylvain has not yet released the source code, nor details of the language he developed.

Alberto Garlassi Creates a Software Defined Radio with an FPGA, Passives

Engineer Alberto Garlassi has created a software-defined radio with a difference: It’s built from nothing more than an FPGA, three resistors, and a capacitor.

“This project has been created as a way to learn Verilog and have some fun with FPGA and SDR. Main goal is to receive AM broadcast stations with as little components as possible,” Alberto writes. “The FPGA chosen, Lattice MachXO2, is also among the simplest components that can be used.

“I was able, with 20 meters of electrical wire as an antenna, to receive stations from thousands of kilometers, located in three continents. Smallest BOM consists of a €30 Lattice MachXO2 breakout board, three resistors, one capacitor, and a speaker. For better performance it is best to add a crystal oscillator — sensitivity and audio quality are better than with the internal oscillator.”

The resulting project is an FPGA-driven direct down conversion (DDC) receiver, in which the analogue-to-digital converter (ADC), mixer, CIC filters, AM demodulator, and pulse-width modulation (PWM) output for audio all defined on the FPGA rather than as discrete components.

Full details are available on Alberto’s Hackaday.io project page.